ASIC verification, explained with working code
From your first covergroup to sign-off reviews: SystemVerilog, UVM, assertions, protocols and SoC verification, explained with code that runs.
Experienced engineer? Start here →
For every level
Learn SystemVerilog one lesson at a time, with code you can run.
Start the SystemVerilog path → Junior engineerGo from UVM concepts to a working environment, step by step.
Start the UVM path → Mid-level engineerDebug playbooks and protocol guides built from real failures and logs.
Open the practical guides → Experienced engineerExperiments, methodology and advanced UVM, without the basics.
Start here →Where to start
From data types and classes to constrained randomization and interprocess communication: the SystemVerilog you use every day in a testbench.
Start the path → 26 lessonsHow a real UVM testbench is built and run: architecture, factory and configuration, stimulus, phasing, reporting, then RAL and phase jumps.
Start the path → 5 lessonsWhy assertions matter, immediate versus concurrent, then worked SVA examples and binding assertions to a design.
Start the path → 4 lessonsCoverage metrics, covergroup options and guidelines for writing coverage that actually closes.
Start the path → 8 lessonsHow verification engineers think, plan and debug: the habits behind every good testbench.
Start the path →Editor's picks
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A repeatable verification debug method: the five-door order, UVM and SystemVerilog tips, waveform tracing, regression triage, and an AI-assisted debug flow.
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UVM testbench architecture in one place: a clear diagram, every component and its job, and a complete working example you can run. Plus SVA, coverage, debug,…
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A UVM scoreboard mismatch has 6 likely causes, and only one is the design. A 5-minute triage, plus 5 planted bugs with real VCS logs to…
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Core skills
Advanced verification
Practical engineering
Every guide is built around a small example that compiles. Read it, run it, change it.
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Async FIFO verification, part 1: Gray-coded pointers, the full and empty flags, a verification plan and a starter UVM bench with real VCS logs.
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randomize() returned 0? Six causes of SystemVerilog randomization failure, how to read the VCS solver log, a 5-minute triage, and a demo with real logs.
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We gave AI a one-page spec and asked for a UVM testbench. Its first draft caught 4 of 4 hidden bugs on VCS. Our hand-written bench…
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A practical 2026 guide to AXI protocol verification: the five channels, handshakes, IDs and ordering, a working UVM agent with SVA and coverage, AXI4 vs AXI5…
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Learn Portable Stimulus (PSS) with runnable DMA and UART examples, what is new in PSS 3.0, and how AI tools help write PSS models. Explained in…
Interview preparation
Written by a verification engineer with more than a decade of experience across Intel, Samsung Semiconductor and startups. Read the story →
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About
The Art of Verification is an engineering-focused publication that explains verification in plain words, with a small example that runs and a link to the bigger picture.
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