AI UVM testbench experiment - The Art of Verification
https://theartofverification.com/ai-uvm-testbench-experiment/

prompt.txt     the exact prompt given to the AI, including the spec
spec.md        the mem16 specification on its own
dut_mem16.sv   the design, with 4 hidden bugs switched on by +BUG=1..4 (0 = clean)
tb_ai_r0.sv    the AI's testbench, first draft, unchanged
tb_hand.sv     the hand-written baseline (from the Practical Verification Debug Guide)

Run (Synopsys VCS, UVM 1.2):
  vcs -full64 -sverilog -ntb_opts uvm-1.2 dut_mem16.sv tb_ai_r0.sv -R +BUG=0
  vcs -full64 -sverilog -ntb_opts uvm-1.2 dut_mem16.sv tb_hand.sv  -R +BUG=0
then +BUG=1 to +BUG=4. If your tool only takes compile options, use +define+BUG=N.
The first line of every log is "mem16: hidden bug = N".
