You are a senior design verification engineer. Write a complete UVM 1.2 testbench in SystemVerilog for the design described in the specification below.

Requirements:
- The design is a module named mem16 with exactly the ports in the specification. It is compiled from a separate file. Do not write or modify the design.
- Put the whole testbench in one file. The top module must be named tb_top and must instantiate mem16, generate the clock and reset, and call run_test().
- Use a UVM test named mem16_test so that run_test("mem16_test") works without command-line arguments.
- The testbench must check the design against the specification and report any mismatch with `uvm_error. A correct design must finish with 0 UVM_ERROR and 0 UVM_FATAL.
- The test must end on its own, within 1 ms of simulated time.
- It must compile and run on Synopsys VCS with the built-in UVM 1.2 library (vcs -sverilog -ntb_opts uvm-1.2).

Reply with only the testbench file, in a single code block, followed by at most 5 short bullet points describing what the testbench checks.

Specification:

# mem16: specification

A 16-word by 32-bit memory with a request/acknowledge handshake.

## Ports

| Port  | Dir | Width | Meaning |
|-------|-----|-------|---------|
| clk   | in  | 1  | Clock, all signals sampled on the rising edge |
| rst_n | in  | 1  | Asynchronous reset, active low |
| req   | in  | 1  | Request |
| we    | in  | 1  | 1 = write, 0 = read |
| addr  | in  | 4  | Word address, 0 to 15 |
| wdata | in  | 32 | Write data |
| ack   | out | 1  | Acknowledge |
| rdata | out | 32 | Read data |

## Behaviour

1. Reset: while rst_n is low, all 16 words become 0, and ack and rdata are 0.
2. A transfer starts when req goes high. The requester holds req, we, addr and wdata stable until it sees ack high.
3. The memory raises ack for exactly one clock cycle, between 1 and 5 clock cycles after the first rising edge at which it sees req high. The delay may differ from transfer to transfer.
4. Write (we = 1): wdata is stored at addr when ack is raised.
5. Read (we = 0): in the cycle ack is high, rdata equals the last value written to addr since reset, or 0 if addr has not been written since reset.
6. After seeing ack high, the requester must drive req low for at least one clock cycle before starting the next transfer.
7. All 16 addresses are valid.
