UVM TLM Explained: Ports, Exports, Analysis Ports and FIFOs
In short: UVM TLM lets components hand whole transactions to each other through ports instead of signals. The component that calls owns a port, the component that does the work owns an imp, and connect() joins them. A uvm_analysis_port is one-to-many: write() is a function, returns at once, and reaches every subscriber (or none). A…