SoC Verification

Verifying systems on chip: flows, key areas, clocks and processor-based designs.

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Assertions | Functional Coverage | Interview Questions | System Verilog | UVM | Verification Fundamentals

Clock Multiplication vs Division: Which to Use and Why
ByThe Art of Verification November 8, 2023July 22, 2026

In short: Designs need many clock frequencies from one reference. Division is simple but only gives integer ratios below the reference and can pile up jitter across a long chain. Multiplication, usually via a PLL, reaches higher frequencies, supports non-integer ratios, and often has lower jitter, which is why it suits high-speed links, CPU cores,…

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UVM

How to Verify Complex RISC-V–based Designs?
ByThe Art of Verification September 23, 2022July 20, 2026

In short: Verifying a RISC-V design has two parts: prove the core is correct and ISA compliant, and prove the whole system built around it works. As the system grows with more cores, peripherals, and custom hardware, RTL simulation alone gets too slow. Transaction-level hardware emulation (ideally on the Accellera SCE-MI standard), with an ISS…

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System Verilog | UVM

Key Areas to consider during SOC Verification
ByThe Art of Verification January 12, 2022July 20, 2026

In short: SoC verification is mostly about integration: the individual IP blocks are already verified, so at the chip level you focus on how they connect and work together. The key areas are pin muxing, protocol checks at block boundaries, reset and boot-up, memory and register access, control and data paths, analog integration, low power,…

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System Verilog | UVM

Clock Monitors in SoC Verification
ByThe Art of Verification August 5, 2021July 26, 2026

In short: A clock monitor is a reusable SystemVerilog/UVM component that watches a clock signal and automatically checks its frequency, duty cycle, and on-the-fly switching, and flags glitches or timeouts. Because it is built as a uvm_monitor inside a uvm_agent, you can plug it into any UVM environment and verify complex clock systems without writing…

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System Verilog | UVM

Mastering the SOC Verification Flow: A Comprehensive Guide
ByThe Art of Verification June 5, 2021July 20, 2026

In short: The SoC verification flow is the end-to-end process of proving a whole chip works once all its blocks are stitched together. It moves through five stages: pull out the features to test, write a verification plan, build the environment and run tests, close functional and code coverage, then sign off. The focus at…

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