In the ever-evolving world of chip design, where circuits dance with logic and transistors tango with electrons, stands a breed of unsung heroes: the ASIC verification engineers. These digital detectives, armed with their arsenal of tests, hunt down bugs with the zeal of Indiana Jones and the precision of a Swiss watchmaker. Today, we delve…
In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an alternative method involves using a multiplied version of the reference clock. This blog post delves into the intricacies of handling clock…
Formal verification and functional verification are two complementary approaches to ASIC verification. Formal verification uses mathematical methods to prove that a design meets its specifications, while functional verification uses simulations to test the design against a variety of scenarios. Formal verification is more rigorous and can find bugs that functional verification may miss, but it…
Introduction: In the realm of Design Verification, debugging stands as a crucial process for uncovering and rectifying issues that may compromise the functionality, reliability, and performance of complex chip designs. While the term “debugging” might imply a scientific approach, it is truly an art form that requires a delicate balance of technical expertise, creativity, and…
Introduction Hey there, fellow ASIC Verification enthusiasts! Welcome to our deep dive into the fascinating world of verification excellence. Ever wondered what’s at the heart of it all? It’s our thought process. Yes, that’s right! Our ability to think strategically, creatively, and methodically is what sets us apart. It’s the engine that drives our work,…
With innovations in technologies and methodology, the benefits of formal functional verification apply in many more areas. If we understand the characteristics of areas with high formal applicability, we can identify not only which blocks are good candidates, but also what portions or functionalities of the blocks will give the greatest return on the time…
I hope you started understanding assertions and their operators well with practical examples. Let’s start learning more operators in this post. Before starting part-2 of assertions operators and their basic examples if you haven’t visited part-1 of basic assertions operators and their examples I highly recommend that please visit that blog post and revise your…
System Verilog assertions always help to speed up the verification process and it’s very powerful and widely used in the ASIC verification. Identifying the right set of checkers in the verification plan and implementing them using effective SV assertions helps to quickly catch the design bugs and ultimately helps in high-quality design. With the ever-increasing…
Immediate assertions use expressions and are executed like a statement in a procedural block. They are not temporal in nature and are evaluated immediately when executed. Immediate assertions are used only in dynamic simulations. Following is an example of a simple immediate assertion that checks “if x and y are always equal”: Concurrent assertions are temporal…
An assertion is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening in the design and occurs during simulation, then also the assertion fails. Following…