Advantages of UVM over SV

UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology in terms of architecting testbenches and test cases, and also comes with a library of classes that helps in building efficient constrained random testbenches easily.

Some of the advantages are listed below:

  1. Modularity and Reusability: The methodology is designed as modular components (Driver, Sequencer, Agents, Env, etc.) and this enables reusing components Horizontal(Same level of Abstraction) or Vertically(from IP to SoC/Chip) across IP level to SoC/Subsystem/chip level verification as well as across projects.
  2. Separating Tests from Testbenches: Tests in terms of stimulus/sequences are kept separate from the actual testbench hierarchy and hence stimulus can be reused across projects.
  3. Sequence methodology: It gives good control on stimulus generation. There are several ways in which sequences can be developed: randomization, layered sequences, virtual sequences, etc. This provides a good controlled randomized stimulus generation capability.
  4. Configuration mechanism: It simplify configuration of objects with deep hierarchy. The configuration mechanism helps in easily configuring different testbench components based upon verification environment using it, and without worrying about how deep any component is in the testbench hierarchy.

Factory mechanism: It simplify modification of components easily. Creating each component using factory enables them to be overridden in different tests or environments without touching the code.