AXI Protocol Explained: Channels, Handshake, Bursts and Cache Coherency

AXI shows up in almost every SoC you’ll ever verify.

And in almost every verification interview.

The good news: it rests on a few simple ideas. Once you see them, the rest of the spec reads like details.

Think of it like a drive-through

Picture a drive-through with separate windows.

• Writing is like dropping off an order with payment:
  • Window 1: say what you want and where it goes (AW, write address).
  • Window 2: hand over the goods (W, write data).
  • Window 3: get your receipt (B, write response).
• Reading is like picking up food:
  • Window 4: say what you want (AR, read address).
  • Window 5: the food comes out (R, read data, with the status on every item).

Each window works on its own. A busy kitchen doesn’t stop the order window from taking the next car. That independence is why AXI is fast.

The five AXI channels

Channel	Direction	Carries	Key signals
AW: write address	Master to slave	Where to write, how many beats, how big	AWADDR, AWLEN, AWSIZE, AWBURST, AWID
W: write data	Master to slave	The data, which bytes are valid, last beat	WDATA, WSTRB, WLAST
B: write response	Slave to master	One status for the whole burst	BRESP, BID
AR: read address	Master to slave	Where to read, how many beats, how big	ARADDR, ARLEN, ARSIZE, ARBURST, ARID
R: read data	Slave to master	The data and a status for every beat	RDATA, RRESP, RLAST, RID

Why does a write need three channels and a read only two? A read’s data and status travel together on R. A write’s data goes one way and its status comes back the other way, so it needs its own return channel, B.

The VALID/READY handshake

Every channel uses the same two wires:

• VALID, from the sender: “I have something for you.”
• READY, from the receiver: “I can take it.”

A beat moves on the clock edge where both are high. Three rules from the Arm specification keep it safe (Arm AMBA AXI specification, IHI 0022):

• Once VALID goes high, it stays high, with the same data, until the transfer happens.
• The sender must not wait for READY before raising VALID.
• The receiver may wait for VALID before raising READY.

The second rule prevents deadlock. If both sides waited for the other, nothing would ever move.

Think of a courier handing you a parcel. VALID is the courier holding the parcel out. READY is you holding your hands open. The parcel changes hands only when both happen. A good courier doesn’t hide the parcel until your hands are open, and doesn’t swap it for a different one while waiting.

// VALID/READY: the master raises VALID and holds it. A beat moves only when both are 1.
module tb;
  logic clk = 0;
  logic valid = 0, ready = 0;
  logic [7:0] data;
  int   sent = 0;
  string note;
  logic [7:0] payload [3] = '{8'hA1, 8'hB2, 8'hC3};
  bit   ready_pattern [10] = '{0, 0, 1, 1, 0, 1, 1, 1, 1, 1};   // slave is busy sometimes

  always #5 clk = ~clk;

  initial begin
    for (int cyc = 0; cyc < 8; cyc++) begin
      // master: drive VALID and DATA without looking at READY
      valid = (sent < 3);
      data  = (sent < 3) ? payload[sent] : 8'h00;
      ready = ready_pattern[cyc];
      @(posedge clk);
      note = (valid && ready) ? "<- transfer" : (valid ? "(waiting)" : "");
      $display("cycle %0d: VALID=%0b READY=%0b DATA=%h %s", cyc, valid, ready, data, note);
      if (valid && ready) sent++;
    end
    $finish;
  end
endmodule

Output (tested on Verilator 5.020, 6 Nov 2026):

cycle 0: VALID=1 READY=0 DATA=a1 (waiting)
cycle 1: VALID=1 READY=0 DATA=a1 (waiting)
cycle 2: VALID=1 READY=1 DATA=a1 <- transfer
cycle 3: VALID=1 READY=1 DATA=b2 <- transfer
cycle 4: VALID=1 READY=0 DATA=c3 (waiting)
cycle 5: VALID=1 READY=1 DATA=c3 <- transfer
cycle 6: VALID=0 READY=1 DATA=00
cycle 7: VALID=0 READY=1 DATA=00

What to notice:

• In cycles 0 and 1, the slave is busy. The master keeps A1 on the bus and waits. It doesn’t drop VALID.
• Three beats moved in six cycles. Two cycles were stalls (backpressure).
• READY high with VALID low (cycles 6 and 7) moves nothing. That’s fine.

Bursts: FIXED, INCR and WRAP

One address phase can carry many data beats. That’s a burst.

Picture a delivery van with one address on the paperwork and many boxes inside. You don’t write a new address on every box. You write the first address and say how many boxes follow.

• AxLEN = number of beats minus 1. AxLEN 3 means 4 beats.
• AxSIZE = bytes per beat, as a power of 2. AxSIZE 2 means 4 bytes.
• AxBURST = how the address moves from beat to beat:

Type	Address each beat	Typical use	Length in AXI4
FIXED	Stays the same	A FIFO behind one address	1 to 16 beats
INCR	Goes up by the beat size	Normal memory	1 to 256 beats
WRAP	Goes up, then wraps to the start of its block	Cache line fills	2, 4, 8 or 16 beats

The three burst types are three ways of dropping off those boxes:

• FIXED: every box goes into the same letterbox. That’s a FIFO behind one address.
• INCR: one box per house, walking down the street.
• WRAP: the houses sit around a small roundabout. You start at the house you care about most, keep going round, and end up back where the circle starts.

The WRAP rule trips people up, so here’s a calculator for all three:

// Beat addresses for FIXED, INCR and WRAP bursts (AXI4 rules).
module tb;
  typedef enum bit [1:0] {FIXED = 0, INCR = 1, WRAP = 2} burst_t;

  // len = AxLEN (beats - 1), size = AxSIZE (bytes per beat = 2**size)
  function automatic void show(string name, bit [31:0] start, int len, int size, burst_t kind);
    int bytes  = 1 << size;
    int beats  = len + 1;
    bit [31:0] lower = (start / (bytes * beats)) * (bytes * beats);  // wrap boundary
    bit [31:0] addr  = (start / bytes) * bytes;                      // aligned start
    string line = "";
    for (int i = 0; i < beats; i++) begin
      line = {line, $sformatf(" 0x%0h", addr)};
      if (kind == INCR) addr += bytes;
      if (kind == WRAP) begin
        addr += bytes;
        if (addr == lower + bytes * beats) addr = lower;            // wrap around
      end
    end
    $display("%-6s start 0x%0h, %0d beats of %0d bytes:%s", name, start, beats, bytes, line);
  endfunction

  initial begin
    show("FIXED", 32'h100, 3, 2, FIXED);   // same address every beat (a FIFO)
    show("INCR",  32'h100, 3, 2, INCR);    // 4 bytes further each beat
    show("WRAP",  32'h38,  3, 2, WRAP);    // 16-byte block 0x30-0x3F, starts in the middle
    $finish;
  end
endmodule

Output (Verilator 5.020):

FIXED  start 0x100, 4 beats of 4 bytes: 0x100 0x100 0x100 0x100
INCR   start 0x100, 4 beats of 4 bytes: 0x100 0x104 0x108 0x10c
WRAP   start 0x38, 4 beats of 4 bytes: 0x38 0x3c 0x30 0x34

The WRAP burst lives in a 16-byte block (4 beats x 4 bytes), from 0x30 to 0x3F. It starts at 0x38, runs to the end of the block, then wraps back to 0x30.

Why would anyone want that? A CPU that misses on address 0x38 wants that word first, so it can carry on. The rest of the cache line follows.

The 4KB rule

A burst must never cross a 4KB boundary (Arm IHI 0022).

Why? Slaves are usually mapped on 4KB pages. A burst that crossed one could start in one slave and end in another, and no single slave could answer for the whole thing.

Treat each 4KB page like a town, each with its own post office. A single delivery run can’t cross the town border, because the next town’s post office never saw the paperwork.

The check is simple: the first byte and the last byte must sit in the same 4KB page. In other words, address bits [31:12] must match.

// Does a burst cross a 4KB boundary? Compare the 4KB "page" of the first and last byte.
module tb;
  function automatic bit crosses_4kb(bit [31:0] addr, int len, int size);
    bit [31:0] last = addr + ((len + 1) << size) - 1;   // last byte the burst touches
    return (addr >> 12) != (last >> 12);
  endfunction

  function automatic void check(bit [31:0] addr, int len, int size);
    bit [31:0] last = addr + ((len + 1) << size) - 1;
    string verdict = crosses_4kb(addr, len, size) ? "CROSSES 4KB" : "ok";
    $display("addr 0x%04h, %3d beats x %2d bytes -> last byte 0x%04h : %s",
             addr, len + 1, 1 << size, last, verdict);
  endfunction

  initial begin
    check(32'h0FF0, 1, 2);    // 8 bytes, ends at 0x0FF7
    check(32'h1FF8, 2, 2);    // 12 bytes, runs past 0x2000
    check(32'h5BA0, 243, 4);  // 244 beats of 16 bytes = 3904 bytes
    $finish;
  end
endmodule

Output (Verilator 5.020):

addr 0x0ff0,   2 beats x  4 bytes -> last byte 0x0ff7 : ok
addr 0x1ff8,   3 beats x  4 bytes -> last byte 0x2003 : CROSSES 4KB
addr 0x5ba0, 244 beats x 16 bytes -> last byte 0x6adf : CROSSES 4KB

The third line is a real case from the forums, covered in mistake 3 below.

Byte strobes and narrow transfers

Think of each data beat as an egg tray with one slot per byte. WSTRB is a sticker on each slot saying “this one has an egg, keep it” or “empty, ignore it”.

• WSTRB has one bit per byte lane. A 1 means “this byte is real, write it”.
• A narrow transfer uses beats smaller than the bus. Say 1-byte beats on a 32-bit bus: each beat uses a different byte lane, and WSTRB shows which one.
• An unaligned start (like 0x101 with 4-byte beats) means the first beat only fills some lanes. WSTRB masks off the bytes before the start address.

Responses: OKAY, EXOKAY, SLVERR, DECERR

Response	Meaning	Who sends it
OKAY	Normal success	The slave
EXOKAY	Exclusive access succeeded	The slave
SLVERR	The slave got the request but failed it	The slave
DECERR	No slave lives at that address	Usually the interconnect

A read gets a response on every beat (RRESP). A write gets one response for the whole burst (BRESP), after the last data beat.

The four responses work like delivery notes. OKAY is “delivered”. EXOKAY is “delivered, and nobody touched your reserved shelf”. SLVERR is “the shop got it but couldn’t stock it”. DECERR is “no shop at that address”, stamped by the sorting office.

IDs, outstanding and out-of-order transactions

A master doesn’t have to wait for one transaction to finish before starting the next. It can have many outstanding at once.

It’s like a busy restaurant. The waiter takes orders from five tables before the first dish comes out. Nobody waits for table 1 to finish eating before table 2 can order.

The ID signals (AWID, BID, ARID, RID) decide what may finish in which order:

• Different IDs may finish in any order. A fast memory can answer before a slow one.
• Same ID must finish in the order sent.

Back to the drive-through: each car gets a ticket color. Cars with different colors can be served in any order. Cars with the same color are served in line.

To check this in a testbench, keep one queue of expected transactions per ID, stored in an associative array. There’s a full tested scoreboard for exactly this in SystemVerilog arrays and queues. And to give each outstanding write its own ID, see unique random values.

Can write data arrive before the write address?

Yes. The channels are independent, so a master may put data on W before, after or together with the address on AW. The master must not wait for AWREADY before raising WVALID, and the slave must cope with data that shows up first (Arm IHI 0022).

Picture a parcel that reaches the depot before its shipping label. The depot holds it until the label arrives, then sends it on. It doesn’t throw it away.

Exclusive access

Exclusive access lets a CPU do a safe read-modify-write without locking the whole bus.

It works like editing a shared document. You open it, make your change and hit save. If someone else saved in between, your save is rejected and you try again. Nobody had to lock the file for everyone else while you worked.

1. Exclusive read (AxLOCK = 1) from an address.
2. Change the value in the CPU.
3. Exclusive write back, same address, same ID.
4. If nobody else wrote that location in between, the slave answers EXOKAY and the write happens. If someone did, it answers OKAY and the write is dropped, so the CPU tries again.

Cache coherency, in plain terms

When two CPUs each keep a copy of the same memory line in their own cache, one of them may change it. Coherency makes sure the other doesn’t keep reading the old copy.

Picture an office with one master notebook in a cabinet (main memory). Each person keeps a photocopy of a few pages on their own desk (their cache), because walking to the cabinet is slow. The trouble starts when two people have a copy of the same page and one of them writes on theirs.

• MESI gives each cache line a state: Modified, Exclusive, Shared or Invalid.
• Snooping means a cache watches (snoops) what others do and updates or drops its own copy.
• ACE (AXI Coherency Extensions) adds three snoop channels to AXI: AC (snoop address), CR (snoop response) and CD (snoop data).
• CHI is Arm’s newer, packet-based protocol for bigger coherent systems.

The MESI states

State	This cache’s copy	Memory	Other caches
Modified (M)	Changed, the only valid copy	Out of date	None
Exclusive (E)	Clean, only copy	Up to date	None
Shared (S)	Clean	Up to date	May also have it
Invalid (I)	Not usable	n/a	n/a

Back in the office: if you scribble on your photocopy (M), everyone else’s copy of that page is now wrong, so they must throw theirs away (I) before you write. If you only read it, several people can hold the same clean copy (S). If you’re the only one with a clean copy (E), you can start writing without asking anyone.

Snoop-based vs directory-based

How does everyone find out that a page changed? Two ways:

• Snooping is shouting across an open office: “I’m changing page 12, throw away your copies!” Easy with five people. Chaos with five hundred.
• A directory is a librarian with a register of who has a copy of each page. She only calls the people on her list.

	Snoop-based	Directory-based
How it finds other copies	Asks every cache (broadcast)	Looks it up in a directory of who holds what
Good for	A few CPUs	Many CPUs, large systems
Cost	Lots of snoop traffic as systems grow	Extra storage for the directory

ACE vs ACE-Lite

Think of ACE as a staff member with their own desk copies, so the office has to keep them in the loop. ACE-Lite is a visitor who only reads from the cabinet. They need to see the latest version, but they keep no copies, so nobody ever has to warn them.

	ACE	ACE-Lite
Has its own cache that others can snoop	Yes	No
Snoop channels (AC, CR, CD)	Yes	No
Typical master	CPU cluster	DMA, GPU or other I/O master that must see coherent data

AXI3 vs AXI4 vs AXI4-Lite

	AXI3	AXI4	AXI4-Lite
Max INCR burst	16 beats	256 beats	1 beat (no bursts)
Write data interleaving (WID)	Yes	Removed	No
Locked transfers	Yes	Removed (exclusive only)	No
IDs and out-of-order	Yes	Yes	No
QoS, region, user signals	No	Yes	No
Typical use	Older IP	Memory, DMA, CPUs	Control and status registers

AXI vs AHB vs APB

	APB	AHB	AXI
Built for	Simple, slow peripherals	Mid-speed shared bus	High-speed memory and CPUs
Transfers in flight	One	One (pipelined address and data)	Many (outstanding)
Separate read and write paths	No	No	Yes
Out-of-order completion	No	No	Yes, with IDs

Think of APB as a shop counter with one clerk serving one customer at a time, AHB as a single-lane road, and AXI as a highway with separate lanes for each direction and many cars at once.

AXI systems still use APB and AHB peripherals through bridges.

Other signals interviewers ask about

• AxCACHE: memory attributes. Can this transfer be buffered? Can it be merged or changed on the way? Should a cache allocate a line for it?
• AxPROT: three protection bits. Privileged or normal, secure or non-secure, instruction or data.
• AxQOS: a 4-bit priority hint for the interconnect.
• AxREGION: lets one slave interface act as several logical regions.
• Low-power: CSYSREQ and CSYSACK let the system ask a peripheral to enter low power. CACTIVE tells the system the peripheral still needs its clock.
• AXI4-Stream: no addresses at all. Just a one-way stream of data with TVALID, TREADY, TDATA and TLAST.
• Widths: the data bus can be 8 to 1024 bits wide. AxSIZE says how many bytes each beat uses, up to the full bus.

Common AXI mistakes (and the fix for each)

These come from real forum threads. Each one is retold in my own words, with a link to the original.

1. Making VALID wait for READY

• What happened: an engineer saw WREADY stay low in the middle of a burst and asked whether the master’s VALID should depend on READY (Arm Community forum).
• Why it matters: the answer, straight from the spec, is no. If the master waits for READY and the slave waits for VALID, nothing ever moves.
• Fix: raise VALID when you have data, hold it until the handshake. READY may depend on VALID, never the other way round.

2. Starting a WRAP burst on an unaligned address

• What happened: in 2009 someone tried to work out a WRAP burst starting at address 55 on a 32-bit bus (Arm Community forum, 2009).
• Why: a WRAP burst must start on an address aligned to the beat size. 55 isn’t a multiple of 4.
• Fix: start at 56 (0x38). Then the beats go 56, 60, 48, 52, which is exactly what the calculator above prints.

3. Checking the 4KB rule with only a modulo

• What happened: in 2020 an engineer’s constraint still let a burst at 0x5BA0, with AWLEN 243 and 16-byte beats, run past a 4KB boundary (Verification Academy, 2020). A 2017 thread hit the same trap (Verification Academy, 2017).
• Why: addr % 4096 only tells you where the burst starts inside its page. You also need to know how far it goes.
• Fix: the offset plus the burst size must fit: addr % 4096 + ((len + 1) << size) <= 4096. Same idea as the tested crosses_4kb() above, which flags this exact case.

4. Mixing bits and bytes in the wrap boundary

• What happened: in a 2018 thread about address 0x24 with 4-byte beats and 4 beats, an answer used bits instead of bytes for the wrap size. A 2025 reply corrected it (Verification Academy, 2018).
• Why: the wrap block is bytes per beat x number of beats. Here that’s 4 x 4 = 16 bytes, not 32 x 4.
• Fix: always work in bytes: 2**AxSIZE x (AxLEN + 1).

5. Assuming write data must wait for the address

• What happened: in 2022 someone asked whether write data can be sent before the write address (Verification Academy, 2022).
• Why it matters: it can. A slave or a testbench model that assumes AW always comes first will hang or drop data on legal traffic.
• Fix: build slaves and slave models to accept W before AW. Test that order on purpose.

AXI and cache coherency interview questions

All the questions engineers ask most, grouped, with short answers.

Channels and handshake

Why five channels instead of one shared bus? So address, data and response move on their own. Reads don’t wait for writes, and a new address can go out while old data is still flowing.

Why does a read have two channels and a write three? Read status rides with the data on R. Write status has to come back the other way, so it gets its own channel, B.

Which channels does the slave drive VALID on? B and R. The master drives VALID on AW, W and AR.

What is “control information”? Everything on the address channel besides the address: length, size, burst type, ID, cache, protection, lock and QoS.

Why must VALID never wait for READY? To avoid deadlock. If both sides waited for each other, nothing would move.

Why must VALID and the data stay stable until the handshake? The receiver may sample on any cycle once it raises READY. If the sender changed its mind, the receiver could take half of one beat and half of another.

Which order of VALID and READY is fastest? READY already high when VALID rises. The beat moves on the very first cycle.

Why is AWREADY often left high by default? The spec recommends it. A slave that’s ready before the address arrives saves a cycle on every transfer.

Why must a master not wait for AWREADY before driving WVALID? Some slaves wait for write data before accepting the address. If the master waited too, both would hang.

Can RVALID come before ARVALID? No. The slave must see the read address handshake first.

Can a read finish in one cycle? No. Read data can only follow the address handshake, so it takes at least two cycles.

Is there a timeout on a handshake? Not in the protocol. A slave may hold READY low as long as it likes. Testbenches add a watchdog to catch hangs.

What does a high-latency slave mean? It takes many cycles before the first data comes back. Outstanding transactions hide that wait.

Bursts and addresses

Why is AXI burst-based and address-first? One address phase can carry up to 256 beats, so the bus spends its time on data, not addresses.

Why is the burst length AxLEN + 1? A burst always has at least one beat, so 0 means 1. All 8 bits stay useful: 1 to 256 beats.

Why are FIXED and WRAP limited to 16 beats while INCR can do 256? WRAP is for cache lines and FIXED is for FIFOs, and neither needs long bursts. INCR is for big memory copies.

Who works out the addresses of later beats? The slave. It only gets the start address, length, size and burst type.

Which burst type is used for cache lines? WRAP, so the word the CPU missed on comes first.

Where are INCR and FIXED used? INCR for normal memory. FIXED for a FIFO or data register at one address.

What happens with an unaligned start on a WRAP burst? It’s not allowed. A WRAP burst must start aligned to the beat size.

Why can’t a burst cross 4KB? Slaves are mapped on 4KB pages. One burst could otherwise touch two slaves.

What if LAST isn’t set on the final beat? That’s a protocol error. A slave that counts on LAST won’t know the burst ended, and the next burst gets mixed up. A checker should flag it.

Is early burst termination supported? No. A master must finish every beat. For writes it can turn the strobes off on the beats it doesn’t need.

Strobes and alignment

Why does AXI need byte strobes? To write some bytes of a beat and leave the rest untouched, without a read-modify-write.

Is a WSTRB of 0110 valid? Yes. Any pattern is allowed, even with gaps.

What does WSTRB mean when WVALID is low? Nothing. It’s ignored.

How do you write all bytes? Set every WSTRB bit to 1.

What is a narrow transfer? A beat smaller than the bus, like 1 byte on a 32-bit bus. Each beat uses a different byte lane.

How do you tell if an address is aligned? It’s aligned if it’s a multiple of the beat size. 0x104 is aligned for 4-byte beats; 0x105 isn’t.

Responses and ordering

Why does a read get a response per beat, but a write only one? Read status travels with each data beat for free. A write needs one answer after the last beat.

Why does DECERR come from the interconnect? No slave answers that address, so the interconnect’s default slave replies for it.

Why allow outstanding transactions? To keep the bus busy while slow slaves work.

Why allow out-of-order responses, and why do IDs matter? A fast slave shouldn’t wait behind a slow one. IDs tell the master which answer is which; same-ID answers stay in order.

How is data integrity ensured? AXI4 has no parity or ECC on the bus; errors come back as SLVERR or DECERR. AXI5 adds optional parity check signals.

Does AXI support AHB and APB devices? Yes, through bridges.

Exclusive access and protection

Why not just lock the whole bus? Locking stops everyone else. Exclusive access lets others keep working and only fails if someone touched the same address.

How does a slave treat an exclusive read? It remembers the address and ID. If it supports exclusives, it answers EXOKAY. If not, OKAY.

What is EXOKAY? The response that says an exclusive access worked.

How is protection provided? With AxPROT: privileged or normal, secure or non-secure, instruction or data.

Cache coherency

Why is coherency needed? Two CPUs can hold copies of the same line. Without coherency, one keeps reading old data after the other changes it.

What are the MESI states? Modified, Exclusive, Shared, Invalid. See the table above.

Snoop-based or directory-based: when do you use each? Snooping for a few CPUs. A directory for many, because broadcasting to everyone stops scaling.

What does ACE add to AXI? Three snoop channels (AC, CR, CD) and extra signals so caches can stay in step.

What is ACE-Lite? For masters without their own cache, like DMA. They see coherent data, but nobody snoops them.

What happens when an address isn’t in the cache? A miss. The cache fetches the whole line from memory, usually with a WRAP burst, and may evict another line to make room. Like finding the fridge empty and going to the shop, then clearing a shelf for what you bring back.

What is cache prefetching? Fetching lines before the CPU asks for them, so they’re already there when it does. Like buying milk before you run out.

Why do cache line fills use WRAP bursts? The CPU gets the word it missed on first and can carry on while the rest of the line arrives.

What to read next

• AXI protocol verification guide: UVM agent, SVA checks and coverage for AXI
• SystemVerilog arrays and queues: includes a tested out-of-order AXI scoreboard
• Unique random values: picking different AWIDs for outstanding writes

References

• Arm, AMBA AXI and ACE Protocol Specification (IHI 0022): channels, handshake rules, bursts, the 4KB rule, IDs, responses, exclusive access, ACE.
• Forum threads linked in the mistakes section (accessed 6 Nov 2026).
• All code tested on Verilator 5.020 on 6 Nov 2026.

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