Understanding with AXI Protocol and Cache Coherency

Most AXI answers fail an interview not because the candidate does not know the signal, but because they cannot explain why the protocol was designed that way. This resource fixes that. Every section states the concept, then answers the why behind it. For wider practice, browse the full set of interview questions, and back your answers with assertions you would write in SystemVerilog or UVM.

A simple way to picture AXI

Think of AXI like a busy post office with separate counters instead of one shared queue. There is one counter to hand in the address for a parcel you are sending, one to drop the parcel itself, and one where a clerk gives you a receipt. For collecting mail there is a counter to give the pickup address and a hatch where items come back. Because the counters are separate, one customer drops off while another picks up, and you state the starting address only once even for a stack of parcels going to the same street. That is AXI: independent channels, address given once per burst, and a receipt to confirm the job.

Key features of the AXI protocol

Before the details, here is what AXI actually gives a designer, and why each feature matters:

• Separate address/control and data phases. The address is sent apart from the data, so the two can pipeline instead of waiting on each other.
• Unaligned transfers using byte strobes. WSTRB lets a transfer start off a natural boundary and still write only the correct bytes.
• Burst-based transactions with only the start address issued. One address covers many beats, cutting address traffic.
• Separate read and write data channels. This supports low-cost Direct Memory Access (DMA), because a DMA engine can read and write at the same time.
• Multiple outstanding addresses. A master can issue several requests before earlier ones finish, hiding slave latency.
• Out-of-order transaction completion. Using ID tags, fast transactions can finish before slow ones.
• Easy addition of register stages. Because channels are one-way and independent, register slices can be inserted for timing closure without breaking the protocol.

The five AXI channels and why there are five

AXI splits every transfer into five one-way channels. Writes use three; reads use two. Each channel carries its own information and uses the same handshake.

Why five channels instead of one shared bus?

• Parallel work. Address and data travel on different wires, so the master can send the next address while data for the previous one is still moving. A single shared bus would force one thing at a time.
• Reads and writes do not block each other. Separate read and write paths mean a slow write does not hold up a read, which raises real throughput.
• Simple, one-way flow control. Each channel is one direction with its own valid/ready pair, so each can run at its own pace and be pipelined independently.
• Cheap timing closure. Because channels are separate and directional, register slices can be dropped into any of them without changing behaviour.

Why does a read have only two channels while a write has three?

• A read response has somewhere to ride. The read result (RRESP) travels attached to each returning data beat on the R channel, so no separate response channel is needed.
• A write result has nowhere to ride until the end. The master finishes sending write data before the slave knows whether the whole burst succeeded, so a dedicated B channel carries that single confirmation back afterwards.
• One response per write burst, not per beat. The slave commits the whole write, then reports once, which keeps the write path efficient.

The valid/ready handshake and why the rules exist

Every channel moves one item of information with the same two signals: the source raises VALID when it has something ready, and the destination raises READY when it can accept. Transfer happens on the clock edge where both are high together.

// Legality rule: once VALID is high it must stay high, with a stable payload,
// until the handshake completes. Shown on the write-address channel.
property p_awvalid_stable;
  @(posedge ACLK) disable iff (!ARESETn)
    (AWVALID && !AWREADY) |=> AWVALID && $stable(AWADDR);
endproperty
a_awvalid_stable: assert property (p_awvalid_stable)
  else $error("AWVALID or AWADDR changed before AWREADY: illegal AXI handshake");

Why must VALID never wait for READY?

• To prevent deadlock. If the source waited for READY and the destination waited for VALID, both would wait forever. The protocol breaks the tie by saying VALID asserts as soon as the source is ready; READY may come before or after.
• To keep channels independent. A master must not wait for AWREADY before driving WVALID. If it did, a slave that accepts data first would stall the whole write.

Why must VALID stay high and the payload stay stable until the handshake?

• So no information is lost. If VALID dropped before READY arrived, the destination could miss the item entirely.
• So the sampled data is trustworthy. Holding the address and control stable means whatever the destination latches on the accepting edge is exactly what the source intended.

Why is AWREADY often recommended to default high? A slave that can usually accept an address immediately saves a cycle on every transfer, because the handshake completes as soon as VALID appears rather than a cycle later.

Bursts, beats, and transactions

These three words get mixed up constantly, so pin them down first, then look at why AXI is burst-based.

Why is AXI burst-based and address-first?

• Less address traffic. The master issues only the start address, and the slave calculates every following beat address. Sending one address for many beats saves bus cycles and power.
• Higher throughput. Once the address is out, back-to-back data beats flow without re-arbitrating for each one.
• Good fit for memory. Real memory and caches move blocks of contiguous data, which maps cleanly onto a burst.

Why is the burst length AWLEN + 1 rather than just AWLEN? Every burst has at least one beat, so a zero-length burst makes no sense. Encoding “length minus one” lets the same field cover a burst of one beat (AWLEN = 0) up to the maximum, using the field efficiently. So AWLEN = 4 means five beats. AxSIZE gives the bytes per beat; five beats of four bytes moves twenty bytes total.

Burst types: FIXED, INCR, and WRAP

• FIXED: every beat uses the same address. Why it exists: it targets a single location repeatedly, such as loading or draining one FIFO or peripheral register.
• INCR: each beat address increases by the transfer size. Why it exists: this is the natural pattern for reading or writing a block of memory.
• WRAP: like INCR, but the address wraps back to a boundary after a set length. Why it exists: it serves cache line fills, delivering the requested critical word first and then wrapping to fill the rest of the line.

Why is FIXED and WRAP limited to short bursts while INCR can be long? WRAP lengths must be a power of two (2, 4, 8, or 16 beats) because the wrap boundary is computed from the line size, and FIXED targets one location so a very long fixed burst has little use. INCR covers ordinary memory blocks, so it is allowed the full range up to 256 beats in AXI4.

The 4KB address boundary rule

A single AXI burst must never cross a 4KB address boundary. This is one of the most asked “why” questions.

• 4KB is the smallest memory page. Address translation works in pages, so staying inside 4KB keeps a burst within one page.
• 4KB is the smallest region that can map to a different slave. If a burst crossed that line, part of it could belong to one slave and part to another.
• A burst carries only one start address. The single-address model cannot describe a transfer split across two slaves, so the protocol forbids the crossing instead.
• The fix is simple. A master that needs data spanning a 4KB boundary splits it into two bursts, one on each side of the line.

Byte strobes, narrow transfers, and unaligned access

WSTRB is the write byte-strobe. Each bit marks one byte lane of the write data bus as valid, with one strobe bit per byte lane, so a 32-bit bus has four WSTRB bits.

Why does AXI need byte strobes at all?

• Partial writes. Software often writes a single byte or halfword into a wider bus. Strobes let the master write only those byte lanes and leave the rest untouched.
• Unaligned and narrow transfers. When the access does not fill the whole bus, strobes mark exactly which lanes hold real data for the current address.
• No read strobe is needed. A read simply returns the addressed bytes and the master picks what it wants, so reads have no strobe.

Why is WSTRB meaningless when WVALID is low? The strobe only describes a data beat that is actually being offered. With no valid data on the bus there is nothing for the strobe to qualify, so its value can be anything and must be ignored. A strobe like 0110 on a 32-bit bus is legal when only the middle two bytes are being written.

What is a narrow transfer, and why does it happen? A narrow transfer is one where the transfer size (AxSIZE) is smaller than the data bus width. It happens when a small master talks on a wide bus. Only the byte lanes that match the current address are active each beat, and for an INCR burst those active lanes shift as the address advances. WSTRB (for writes) shows which lanes are live.

How is an address decided aligned or unaligned? An access is aligned when the start address is a whole multiple of the transfer size. If AxSIZE is four bytes, an address of 0x1004 is aligned but 0x1002 is unaligned. For unaligned starts, the byte lanes and strobes on the first beat cover only the valid bytes, and the transfer continues normally from there.

Responses: OKAY, EXOKAY, SLVERR, DECERR

Both RRESP (read) and BRESP (write) report the outcome of a transfer. There are four values:

Why does a read give a response per beat but a write gives only one for the whole burst?

• Each read beat can independently succeed or fail. Data comes back beat by beat, so each returned item carries its own RRESP.
• A write is only known good at the end. The slave cannot judge the whole write until every beat has arrived, so it reports once on the B channel with BRESP.
• One write response saves traffic. Acknowledging every write beat would waste bandwidth for no extra information.

Why does DECERR come from the interconnect, not a slave? Only the interconnect’s address decoder knows the full memory map. If no slave owns the target address, no slave can answer, so the decoder itself returns DECERR. A SLVERR, by contrast, means a real slave was reached but rejected the access. If a slave hits an error midway through a read burst, the remaining beats are still returned to keep the beat count correct, usually each carrying the error response.

Outstanding and out-of-order transactions

AXI lets a master issue several addresses before earlier ones finish; these are outstanding transactions. Responses carry an ID tag (AxID), which allows out-of-order completion.

Why allow outstanding transactions?

• To hide latency. External memory is slow. Issuing more requests while waiting keeps the slave busy instead of idle, so total throughput climbs.
• To keep pipelines full. A master does not have to stop and wait after each access.

Why allow out-of-order responses, and why do ID tags matter?

• Fast results need not wait for slow ones. A quick access can return before an earlier slow one, which raises efficiency.
• Same ID means same order. Transactions that share an AxID must complete in order, so a master can rely on ordering when it needs to.
• Different IDs may reorder. Independent streams tagged with different IDs are free to finish in any order.
• The interconnect keeps IDs unique. It adds extra bits to each master’s ID, so two masters using the same ID number never clash.

Why write data is treated as buffered

A write is often called buffered because the interconnect or an intermediate slave may accept and store the write data, then return the response before the data reaches its final destination.

• Why do this? It lets a master move on quickly instead of waiting for slow end memory, which improves performance.
• What is the catch? An early response means “accepted,” not necessarily “written to final memory,” so a system that needs strict ordering uses non-bufferable settings or barriers.

WLAST, RLAST, interleaving, and the interconnect

• WLAST and RLAST mark the final beat of a write or read burst. Why they exist: the slave and master must know when a burst ends, since only the start address was sent. A master must never assert WLAST in the middle of a burst, because it declares the burst finished.
• Interleaving lets read data from different transactions return mixed together, sorted by ID. Why it exists: a slave with several outstanding reads can return whichever data is ready first rather than stalling.
• An interconnect is the fabric that routes transactions between masters and slaves and decodes addresses. Why it matters: it is where arbitration, ID widening, and address decoding happen. Common topologies are shared bus, crossbar, and point-to-point.
• Point-to-point means a direct link between exactly one master and one slave with no sharing, used when a path needs guaranteed bandwidth.

Exclusive access and why locks need it

Exclusive access is how AXI supports locks and semaphores across masters without freezing the bus.

• How it works. A master does an exclusive read, then an exclusive write to the same address. The slave returns EXOKAY on the write only if nothing else wrote that location in between; otherwise it returns OKAY and the exclusive write is treated as failed.
• Why not just lock the whole bus? Locking the bus for a read-modify-write would block every other master and kill throughput. Exclusive access achieves the same safety by detecting interference instead of preventing all access.
• What the master does on failure. If the exclusive write fails, the master simply retries the read-modify-write, which is the standard pattern for atomic updates.

Cache coherency, in plain terms

Cache coherency means every cached copy of a memory address agrees on the current value. When several masters each keep a local cache, the same address can sit in more than one cache at once.

Why is coherency needed?

• Stale data causes wrong results. If one master writes its cached copy and another keeps reading an old copy, the two disagree and the program misbehaves.
• Multi-core systems share memory. Modern SoCs have several masters working on the same data, so keeping copies in step is essential.
• System software decides what is cacheable. Memory attributes (carried by signals such as AxCACHE) and software policy mark which regions may be cached, so hardware knows where coherency rules apply.

Why do cache line fills use WRAP bursts? On a cache miss the master needs the exact word it asked for as soon as possible, then the rest of the line. A WRAP burst delivers that critical word first and wraps around to fill the remainder, so the master resumes work without waiting for the whole line. If the requested address is higher than the wrap boundary, the burst still wraps back to the boundary and continues, which is exactly the cache-line behaviour intended.

What happens when an address is not in the cache? The master gets a cache miss and issues a read (often a WRAP burst) to main memory to fetch the line, updates its cache, and then completes the access. If the address is not cacheable at all, the access simply goes straight to memory.

Cache coherency in practice: MESI, snooping, and ACE

The section above explains why coherency is needed. This one explains how real systems actually keep caches in agreement, which is what a multi-core SoC interview usually digs into.

The MESI cache states

Every line in a coherent cache carries a state. The common model is MESI, named after its four states. Some systems add an Owned state, giving MOESI.

The rule that makes coherency work: a cache may only write a line when it holds it in Modified or Exclusive, meaning it has the sole copy. Before writing a Shared line, it must tell the others to drop their copies, which moves this cache to Exclusive first. That single rule prevents two caches from writing the same address at once.

Snoop-based versus directory-based coherency

• Snoop-based (broadcast). When a master needs a line, it broadcasts a request and every other cache checks (snoops) whether it holds that line and responds. Simple and fast for a small number of masters, but the broadcast traffic grows quickly as masters are added.
• Directory-based. A central directory records which caches hold each line, so a request goes only to the caches that actually have it, not to everyone. This suits large systems with many masters because it avoids broadcast storms, at the cost of extra directory storage.

ACE and ACE-Lite: coherency on top of AXI

Plain AXI has no way to ask another cache what it holds. ARM added the AXI Coherency Extensions (ACE) to solve this. ACE keeps the five AXI channels and adds three snoop channels so the interconnect can talk to each cache.

Two flavours exist, and knowing the difference is a common question:

• ACE (full). For masters that have their own coherent cache, such as CPU clusters. They both issue coherent requests and answer snoops.
• ACE-Lite. For masters that have no cache of their own but must read coherent data correctly, such as a DMA engine or GPU. They issue coherent reads and writes but are never snooped, because they hold nothing to snoop.

ACE also defines named transaction types that map onto the MESI moves. A few you should recognise:

So a CPU that wants to write a line it currently shares issues MakeUnique or ReadUnique, the interconnect snoops the other caches over AC, they invalidate their copies and answer on CR, and only then does the writing cache move to Modified. That is coherency in action.

AxCACHE, QoS, and the AXI family

AxCACHE memory attribute bits

AxCACHE is a four-bit field on the address channel that tells the system how a region may be cached and buffered. Getting these right is what keeps coherent and device memory behaving differently.

Device memory (for example a peripheral register) is marked non-cacheable and often non-bufferable so accesses are not reordered or merged, while normal memory is marked cacheable so it benefits from caching.

QoS and region signals

• AxQOS is a four-bit quality-of-service value. A master sets it to hint how urgent a transaction is, and the interconnect can use it to prioritise one master over another during arbitration.
• AxREGION is a four-bit region identifier that lets one slave interface present several logical regions, so the slave can decode a region without extra address bits.

The AXI family: full AXI, AXI-Lite, and AXI-Stream

• Full AXI4 is the high-performance memory-mapped bus with bursts, outstanding transactions, and all five channels. Use it for CPUs, DMA, and memory paths.
• AXI4-Lite is a cut-down memory-mapped version with single transfers only, no bursts, and a fixed data width. Use it for simple control and status registers, where the extra complexity of full AXI is not worth it.
• AXI4-Stream has no addresses at all; it is a one-way data flow for streaming, such as video pixels or samples between processing blocks. Use it when data flows continuously and there is nothing to address.

Low-power and protection signals

• Low-power interface signals let a component request that a peripheral enter or exit a low-power state in an orderly way, so power can be saved without losing in-flight transactions.
• AxPROT carries protection attributes (privileged or normal, secure or non-secure, instruction or data) so a slave can enforce access permissions. Why it exists: security and privilege separation need the bus to say who is asking.

More AXI concepts and quick answers

These are the shorter, frequently asked points from the classic AXI question set, grouped by topic with the reason behind each answer.

AXI versus AHB and APB

• Does AXI support existing AHB and APB interfaces? Yes, through bridges. An AXI interconnect can talk to legacy AHB or APB slaves using an AXI-to-AHB or AXI-to-APB bridge, so older IP still works in an AXI system.
• Advantages of AXI over AHB. AHB uses a single shared pipeline with one outstanding transfer at a time. AXI adds separate channels, bursts with only a start address, multiple outstanding transactions, out-of-order completion, and unaligned transfers. The result is far higher throughput, which is why AXI is used for high-performance paths and APB stays for simple low-speed peripherals.

Bus widths and transfer size limits

• Minimum and maximum data bus width. The AXI data bus width is a power of two, from 8 bits up to 1024 bits. A design picks a width to match the bandwidth it needs.
• Restriction on the size of any transfer. AxSIZE (bytes per beat) must not be larger than the data bus width, because a single beat cannot carry more bytes than the bus has lanes.
• Maximum data in a single burst. In AXI4, an INCR burst can be up to 256 beats. The largest single transaction is therefore 256 beats multiplied by the bytes per beat, as long as it does not cross a 4KB boundary.

Channels, buses, and control information

• Difference between a channel and a bus. A bus is the physical set of wires. A channel is a logical group of those wires plus its own valid/ready handshake that carries one kind of information in one direction. AXI has five channels; they are given different names because each has a distinct role and its own flow control.
• Which channels are exclusive to the slave? The write-response (B) and read-data (R) channels are driven by the slave back to the master. The address and write-data channels are driven by the master.
• What is control information? It is everything sent with the address that describes the access: burst length (AxLEN), size (AxSIZE), burst type (AxBURST), protection (AxPROT), cache attributes (AxCACHE), lock type (AxLOCK), and the ID (AxID).
• Difference between ARVALID, ARADDR, and RVALID. ARADDR is the read address value. ARVALID says that read address is valid and can be accepted. RVALID says the slave has read data ready on the R channel. So ARVALID guards the address going out, and RVALID guards the data coming back.

Handshake ordering and one-cycle transfers

• Which order of VALID and READY is most efficient? The fastest case is when READY is already high before VALID arrives, so the transfer completes the moment VALID asserts. Defaulting AWREADY and ARREADY high when a slave can accept is a common way to get this.
• Can a read complete in one cycle? Yes. If ARVALID and ARREADY handshake, and the slave already has RVALID data ready with RREADY high, a single-beat read can finish quickly. In practice memory latency usually adds cycles.
• Can RVALID be asserted before ARVALID? No. A slave must not return read data before it has accepted the read address, because it does not yet know what to read. Read data always follows an accepted read address.
• Why must a master not wait for AWREADY before driving WVALID? The write-address and write-data channels are independent. If the master waited, a slave that is ready to take data first would stall, and two sides each waiting on the other can deadlock.

LAST, interconnect, and latency

• What if LAST is not asserted after the final transfer? The burst is considered unfinished. The slave keeps expecting more beats, which stalls the channel; a protocol checker or timeout in the environment flags this as an error.
• Is there a timeout on channel handshake in AXI? The protocol itself defines no timeout; VALID and READY may wait as long as needed. Real systems add their own watchdog timeouts in the interconnect or verification environment to catch a hung handshake.
• Major actions done by the interconnect. It decodes the address to pick the target slave, arbitrates between masters competing for the same slave, routes each channel to and from the right port, and widens IDs so masters do not clash.
• What does high latency (or a high initial latency device) mean? It is a slave that takes many cycles to return its first data, such as external DRAM or a device behind several register stages. Outstanding transactions exist precisely so a master can keep working while such a slave responds.
• Which component calculates the addresses of later beats in a burst? The slave (or its AXI interface) computes each beat address from the start address, AxSIZE, and AxBURST, since only the start address is sent.

Byte lanes, strobes, and WRAP address calculation

• Upper byte lane and lower byte lane. For any transfer the active bytes sit between a lower byte lane (the first valid byte position) and an upper byte lane (the last). These come from the address and AxSIZE, and they tell the slave which lanes carry real data.
• Is a WSTRB of 0110 valid? Yes on a 32-bit bus, when only the middle two bytes are being written. Strobes do not have to be contiguous, though real accesses usually are.
• What is WSTRB when WVALID is low? It has no meaning and can be any value, because there is no valid data beat for it to qualify.
• How do you set all WSTRB bits to 1? Drive every strobe bit high, which writes all byte lanes. This is the normal case for a full-width aligned write, for example 0xF on a 32-bit bus or 0xFF on a 64-bit bus.
• How to calculate the address in a WRAP burst. The wrap boundary is the start address rounded down to (number of beats multiplied by bytes per beat). The address increments like INCR until it reaches the boundary plus the wrap size, then it wraps back to the boundary. If the first address is higher than the wrap boundary, the burst still wraps back once it reaches the top, which is exactly how a cache line fills starting from the critical word.
• What happens with an unaligned address on a WRAP burst? WRAP bursts must use aligned addresses by rule, because the wrap maths depends on alignment. An unaligned WRAP request is a protocol violation.
• Which burst type supports cache line access? WRAP, because it fetches the critical word first and wraps to fill the rest of the line. INCR and FIXED do not wrap.
• Where can INCR and FIXED bursts be used? INCR suits blocks of memory; FIXED suits repeated access to one location such as a single FIFO or register.

Data integrity, early termination, and response detail

• How is data integrity ensured on AXI? Through strict handshake rules (VALID and payload held stable until accepted), correct byte strobes, and a response on every transaction. Many systems add parity or ECC on the data buses and protocol checkers or assertions to catch any rule break.
• Is Early Burst Termination (EBT) supported in AXI? No. Unlike some older buses, AXI4 does not allow a master to cut a burst short. The full number of beats set by AxLEN must complete. To move less data, a master issues a shorter burst in the first place. On reads, a slave error is reported per beat while remaining beats still complete to keep the count correct.
• Importance of RRESP and BRESP. They tell the master whether each access worked. Without them a master could not tell a good write from a silently dropped one, so they are essential for error handling and for exclusive access (EXOKAY).
• Significance of AWSIZE and AxLEN. AWSIZE sets how many bytes move per beat; AxLEN sets how many beats. Together they define the total data moved and let the slave compute every beat address.
• Significance of AxBURST. It selects FIXED, INCR, or WRAP, which tells the slave how to compute each following address.

Cache coherency details

• Role of system software in cache address allotment. Software sets up the memory map and marks which regions are cacheable, shareable, or device memory. Hardware then applies coherency rules only where software said caching is allowed.
• What is cache prefetching? Fetching data into the cache before the master actually asks for it, based on a predicted access pattern. It hides memory latency when the guess is right, at the cost of some wasted bandwidth when it is wrong.
• Purpose of RA and WA. RA (Read-Allocate) and WA (Write-Allocate) are cache attributes carried in AxCACHE. Read-Allocate brings a line into cache on a read miss; Write-Allocate brings a line in on a write miss. They tell the system when to fill the cache.
• What happens if an address is not present in the cache? That is a cache miss. The master fetches the line from memory (often a WRAP burst), updates its cache, then completes the access. Non-cacheable addresses go straight to memory.

Exclusive access scenarios and low-power

• Master1 does EX-READ, then Master2 does EX-READ to the same address before Master1 finishes. Both exclusive reads are allowed; several masters may hold an exclusive monitor on the same location at once. The result is decided at the exclusive write stage.
• Master1 does EX-READ, Master2 does a normal write to that address, then Master1 tries EX-WRITE. Master1 exclusive write fails and returns OKAY instead of EXOKAY, because the location changed after the exclusive read. Master1 then retries its read-modify-write.
• How does a slave treat an EX-READ? It records that the master is monitoring that location, returns the data, and later checks at the exclusive write whether the location was modified in between.
• Low-power interface signals in AXI3 and AXI4. A low-power handshake lets a component ask a peripheral to enter or leave a low-power state in an orderly way, so no in-flight transaction is lost while power is saved.
• How is a protection mechanism provided? AxPROT carries privileged-or-normal, secure-or-non-secure, and instruction-or-data bits, so a slave can allow or reject an access based on who is asking.

Worked examples

Concepts stick better with real numbers. Here are the calculations and sequences that come up most often, worked out step by step.

Example 1: WRAP burst address calculation

Take a 4-beat WRAP burst of 4-byte words (AxSIZE = 4 bytes, AxLEN = 3, AxBURST = WRAP) starting at address 0x24. The wrap size is beats multiplied by bytes, which is 4 x 4 = 16 bytes. The wrap boundary is the start rounded down to a multiple of 16, which is 0x20. The address increments by 4 each beat and wraps back to 0x20 after reaching the top of the 16-byte block:

This is exactly how a cache line fetch delivers the requested word first (0x24) and then wraps to fill the rest of the line, so the CPU can resume as soon as its word arrives.

Example 2: splitting a burst at a 4KB boundary

Suppose a master wants an INCR read of 8 beats of 4 bytes (32 bytes) starting at 0xFF0. The 4KB boundary here is 0x1000. The access runs 0xFF0, 0xFF4, 0xFF8, 0xFFC, then the next address would be 0x1000, which crosses the boundary. Because a single burst cannot cross 4KB, the master must split it:

Two legal bursts replace one illegal one, and together they move the same 32 bytes.

Example 3: one write burst, step by step

Here is the channel activity for a 2-beat INCR write, showing how the three write channels interact and where the single response lands:

Notice the address goes out once, the data follows on its own channel, WLAST marks the end, and a single B response confirms the burst.

Example 4: a narrow transfer

A 32-bit master writes on a 64-bit data bus, so each beat is narrower than the bus (AxSIZE = 4 bytes on an 8-byte bus). For an INCR burst starting at 0x00, only the byte lanes matching the current address are active each beat:

The active lanes shift with the address, and WSTRB always marks which half of the wide bus carries real data.

Example 5: exclusive access read-modify-write

This is how a master performs an atomic update of a shared counter using AXI exclusive access. The exclusive write only succeeds (EXOKAY) if nothing wrote the location between the exclusive read and write; otherwise the master retries.

// Atomic increment of a shared counter using AXI exclusive access.
// AxLOCK = EXCLUSIVE marks the accesses as an exclusive pair.
task automatic atomic_increment(input bit [31:0] addr);
  bit [31:0] value;
  bit        success;
  do begin
    // 1) Exclusive read: also arms the slave's exclusive monitor
    axi_read(.addr(addr), .lock(EXCLUSIVE), .data(value));

    // 2) Modify locally
    value = value + 1;

    // 3) Exclusive write: EXOKAY only if no other master wrote addr
    //    in between; OKAY means it failed and we must retry
    axi_write(.addr(addr), .lock(EXCLUSIVE), .data(value), .resp(bresp));
    success = (bresp == EXOKAY);
  end while (!success);
  $display("Atomic increment done, new value = %0d", value);
endtask

If two masters race, one gets EXOKAY and commits; the other sees its location changed, gets OKAY, and loops to try again. No bus lock is held, so other traffic keeps flowing.

Example 6: an AXI covergroup for verification

Because this is a verification blog, here is what you would actually write to measure whether your AXI stimulus exercised the interesting cases. This covergroup samples one address-channel transaction and crosses the key attributes.

// Functional coverage for an AXI write-address transaction.
// Sample this in the monitor each time an AW handshake completes.
class axi_aw_coverage;
  bit [1:0]  burst;   // 0=FIXED, 1=INCR, 2=WRAP
  bit [7:0]  len;     // AWLEN: beats minus one
  bit [2:0]  size;    // AWSIZE: log2(bytes per beat)
  bit [1:0]  resp;    // BRESP seen for this transaction

  covergroup cg_aw;
    cp_burst: coverpoint burst {
      bins fixed = {0};
      bins incr  = {1};
      bins wrap  = {2};
    }
    cp_len: coverpoint len {
      bins single   = {0};
      bins short_b  = {[1:15]};
      bins long_b   = {[16:255]};
    }
    cp_size: coverpoint size {
      bins byte_s  = {0};
      bins half_s  = {1};
      bins word_s  = {2};
      bins wide_s  = {[3:7]};
    }
    cp_resp: coverpoint resp {
      bins okay   = {0};
      bins exokay = {1};
      bins slverr = {2};
      bins decerr = {3};
    }
    // Did we see every burst type at every length class?
    x_burst_len: cross cp_burst, cp_len;
  endgroup

  function new();
    cg_aw = new();
  endfunction
endclass

Running constrained-random traffic against this covergroup shows at a glance whether the tests actually hit FIXED, INCR, and WRAP across single, short, and long bursts, and whether every response type appeared. Holes here point straight to stimulus you still need.

Expected output, in plain words: for the atomic increment, a clean run prints the new counter value once the exclusive write returns EXOKAY; under contention it simply loops until it wins. For the covergroup, a report shows the percentage of bins hit per coverpoint and cross. Note: these describe the intended behaviour from a read of the code and the IEEE and AMBA rules, not captured runs from a specific simulator, so confirm on your own tool or on EDA Playground.

Common AXI misconceptions to avoid

• Thinking VALID waits for READY. VALID asserts as soon as the source is ready; making it depend on READY risks deadlock.
• Forgetting AWLEN is length minus one. AWLEN = 4 is five beats, not four.
• Letting a burst cross 4KB. Split it into two bursts instead.
• Assuming one write response per beat. A write burst gets one BRESP for the whole burst; only reads respond per beat.
• Reading WSTRB when WVALID is low. It is meaningless then and must be ignored.
• Confusing SLVERR and DECERR. SLVERR is a real slave reporting an error; DECERR is the decoder saying no slave exists at that address.

To turn this reading into interview readiness, practise explaining each “why” out loud, then work through related interview questions and back your answers with assertions-style protocol checks you would write in SystemVerilog.

Frequently asked questions

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