The Practical Verification Debug Guide: A Repeatable Method (+ AI-Assisted Debug)
A repeatable verification debug method: the five-door order, UVM and SystemVerilog tips, waveform tracing, regression triage, and an AI-assisted debug flow.
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How UVM RAL works?
In short: UVM RAL (Register Abstraction Layer) is a labelled remote control for the registers inside your chip. Your test reads and writes registers by name, like regmodel.uart.baud_div.write(…), and RAL turns each call into the correct bus activity. It also keeps a mirror copy of every register so your checks always know the expected value….
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How to Build UVM Environment Part – 4
In short: This is the final part of building a UVM environment for the pipe design. Here we add the test, pass the real interface down to every component through the configuration database, add a coverage collector, build the top module that ties the design to the testbench, and finally run the first simulation. By…
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How to Build UVM Environment Part – 3
In short: This is part three of building a UVM environment for the pipe design. Here we add the monitor that watches the pins, wrap the driver, sequencer, and monitor into an agent, and build a scoreboard that checks the results against a small reference model. We then group everything into an environment. After this…
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How to build UVM Environment Part – 2
In short: This is part two of building a full UVM environment for the pipe design. Here we finish the driver so it actually wiggles the pins, add the sequencer, and write several sequences: a single packet, many packets, and a directed case. We also explain the handshake between a sequence and the driver, so…
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How to build UVM Environment Part – 1
In short: This is part one of a four part series where we build a full UVM environment, step by step, to verify a small design. In this part we study the design under test (a two channel pipe), write its SystemVerilog interface, and create the transaction (the data packet) that will carry stimulus and…
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Basic Assertions Examples Part-2
In short: This is part two of the SystemVerilog assertion operators tour. It covers the sampled-value functions $stable and $past, the disable iff reset guard, and the three repetition operators: consecutive [*m], goto [->m], and non-consecutive [=m]. Each is shown with a small property and its pass and fail cases. If you have not seen…
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Basic Assertions Examples Part-1
In short: This is a hands-on tour of SystemVerilog assertions examples using the most-used building blocks: the delay operator ##, overlapping |-> and non-overlapping |=> implication, delay ranges ##[m:n], and the edge detectors $rose and $fell. Each one is shown with a small property, when it passes, and, more importantly, when it fails. Good assertions…
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Reset Testing using Phase Jump in UVM
In short: Reset testing checks that your whole verification environment reacts correctly when reset is applied in the middle of activity. UVM makes this clean with run-time sub-phases (pre_reset, reset, post_reset, configure, main, shutdown) that run in parallel with the run phase, plus a phase jump feature. You drive traffic in the main phase, assert…
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How to generate an array of unique random values
In short: To generate an array of unique random values in SystemVerilog, mark the array rand and add one unique constraint: constraint c { unique {arr}; }. The solver then fills every element with a different value. You can also list extra values inside the braces to keep those out of the set, which is…
