In short: dist makes some random values come up more often than others. := gives the weight to every value in a range, so a wider range gets more in total. :/ gives the weight to the range as a whole and splits it evenly. Weights are shares, not percentages. Other constraints always win over…
In short: Directed testing writes one test per scenario you already know about. Constrained random verification (CRV) lets the simulator generate many legal, varied scenarios from a small set of rules, so it also finds bugs nobody thought to look for. Most real projects use both: CRV first to cover wide ground and catch corner…
In short: A semaphore in SystemVerilog controls access to a shared resource by handing out a fixed number of keys. A process calls get() to take one or more keys before using the resource and put() to return them when done. If no key is free, get() blocks until one is returned; try_get() checks without…
In short: SystemVerilog has four kinds of unpacked array. A fixed array has a size set when you write the code. A dynamic array gets its size at run time with new[]. An associative array only stores the keys you actually use, which suits sparse data like memory. A queue grows and shrinks at either…
In short: Encapsulation means keeping a class’s data and the code that changes it together, and controlling who may touch that data from outside. In SystemVerilog you do this with access qualifiers: members are public by default (open to everyone), local limits access to methods of the same class only, and protected works like local…
