In short: Use logic for almost every signal in SystemVerilog. It holds 4 states (0, 1, X, Z) and takes either one assign or procedural writes. reg is just the old name for the same thing. Use wire only when a signal has more than one driver, like a shared bus or an inout port….
In short: A static class property is shared by every object of the class: there is one copy, not one per instance. A static method belongs to the class rather than to any object, so you call it with the class scope operator (ClassName::method()) without creating an instance, and it can only touch static members….
In short: Lifetime decides how many copies of a variable exist. A static variable has one copy, created once and shared by every call; it remembers its value between calls. An automatic variable gets a fresh copy every time the task or function is called, and it disappears when the call ends. Tasks and functions…
In short: A virtual interface is a pointer (a handle) to a real, physical interface in SystemVerilog. Testbench classes are created and destroyed at run time (they are dynamic), while an interface with its wires is fixed at elaboration (it is static). A class cannot hold a static interface directly, so it holds a virtual…
In short: Polymorphism lets the same call run different code depending on the actual object type behind a handle. In SystemVerilog the run-time form uses virtual methods. If a base-class method is virtual, calling it through a base handle that points at a derived object runs the derived version. Once a method is virtual it…
In short: A virtual method can be overridden in a child class, and the call is resolved by the actual object type at run time, not by the handle type. That is polymorphism. A pure virtual method goes a step further: it is only a prototype with no body, declared inside a virtual (abstract) class,…
In short: The streaming operator in SystemVerilog reshapes data between a single vector and a group of values. Use >> to stream left to right and << to stream right to left. “Pack” squeezes several fields into one wide vector or byte queue, and “unpack” spreads a vector back out into fields. It is the…
In short: Inheritance lets one class (the child) reuse the fields and methods of another class (the parent) using the extends keyword. The child gets everything the parent has, can add new members, and can replace a parent method by overriding it. Mark methods virtual so the right version runs when you call through a…
In short: Plusargs are switches you add to the simulator’s run command, each starting with +, like +DEBUG or +SEED=42. Your code reads them at run time, so you can change a test’s behaviour without recompiling. $test$plusargs(“DEBUG”) tells you whether a switch is there. $value$plusargs(“SEED=%d”, seed) reads the value after it. Always set a default…
In short: The difference between ifdef and plusargs is when they act. An ifdef is a compile time macro: it decides which code is built into the image, so changing it needs a recompile, but the excluded code is truly gone. A plusarg is a run time switch: the whole design is compiled once and…
