In short: The SoC verification flow is the end-to-end process of proving a whole chip works once all its blocks are stitched together. It moves through five stages: pull out the features to test, write a verification plan, build the environment and run tests, close functional and code coverage, then sign off. The focus at…
In short: A fork…join block runs its statements in parallel. The three flavours differ in when the parent thread continues: join waits for all spawned threads, join_any waits for the first one to finish, and join_none waits for none and moves on at once. Two helpers go with them: wait fork blocks until all child…
In short: A shallow copy duplicates only the top-level fields of an object. If the object holds a handle to another object, the copy shares that same inner object, so changing it through one handle affects both. A deep copy duplicates the top-level fields and also builds fresh copies of every nested object, so the…
In short: The this keyword is a built-in handle that refers to the current object, the specific instance whose method is running. Its most common use is inside a constructor or method when a parameter has the same name as a class field: this.x = x; means “set this object’s field x to the parameter…
In short: In SystemVerilog, logic is a 4-state data type (0, 1, X, Z) that replaces the old Verilog reg in most cases. It can be driven by one procedural block or one continuous assignment, so you no longer have to choose between reg and wire for single-driver signals. Use logic for almost every signal…
In short: A static class property is shared by every object of the class: there is one copy, not one per instance. A static method belongs to the class rather than to any object, so you call it with the class scope operator (ClassName::method()) without creating an instance, and it can only touch static members….
In short: In SystemVerilog, a variable’s lifetime decides when its memory is created and freed. A static variable is created once and lives until the simulation ends, so every call shares the same copy. An automatic variable lives on the stack: a fresh copy is made each time you enter the task, function, or block,…
In short: A virtual interface is a pointer (a handle) to a real, physical interface in SystemVerilog. Testbench classes are created and destroyed at run time (they are dynamic), while an interface with its wires is fixed at elaboration (it is static). A class cannot hold a static interface directly, so it holds a virtual…
In short: Polymorphism lets the same call run different code depending on the actual object type behind a handle. In SystemVerilog the run-time form uses virtual methods. If a base-class method is virtual, calling it through a base handle that points at a derived object runs the derived version. Once a method is virtual it…
In short: A virtual method can be overridden in a child class, and the call is resolved by the actual object type at run time, not by the handle type. That is polymorphism. A pure virtual method goes a step further: it is only a prototype with no body, declared inside a virtual (abstract) class,…