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In the intricate world of ASIC Verification, the SOC Verification Flow is a cornerstone process that necessitates both expertise and experience. Many people may not fully understand what sets a system-on-chip (SoC) apart from other semiconductor devices. Within the realm of electronic design automation (EDA), the term “SoC” is often used without a clear definition or explanation […]
Continue ReadingFork..Join: Fork…Join construct of System Verilog actually enables concurrent execution of each of its statements/threads/processes. This feature is most widely used for forking parallel processes/threads in System Verilog Test Benches. System Verilog came up with new and advanced flavors of fork join construct which adds a lot of value for implementers. Fork..Join_any Fork..Join_none Let’s start […]
Continue ReadingShallow Copy: As we know that Classes contains Properties and Methods. A Class may also contain other Class Instantiation as a part of it. All these variables inside a Class got initialized once the Class is constructed. How does that happen, lets see using the following example: Here we are having two Classes named “Class […]
Continue ReadingConcept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept. The this keyword is an implicit argument to a method that refers to the current object. Let’s understand this concept with the following example. In above example we can […]
Continue ReadingBefore we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. A wire is a data type that can model physical wires to connect two elements and It should only be driven by continuous assignment statement and cannot hold any value if not driven. “Reg” in Verilog […]
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Introduction In the world of ASIC Verification, understanding the intricacies of various programming constructs is paramount. Today, we’ll delve deep into the concept of STATIC properties and STATIC methods in SystemVerilog, their significance, and their practical applications. 1. When to Use STATIC Properties and STATIC Methods STATIC properties are particularly useful when we need to share data across all […]
Continue ReadingStatic: For a variable static lifetime is, its memory never de-allocated until simulation ends. Automatic: For a variable Automatic lifetime is, it is stack storage of variable (for multiple entries to a task, function, or block, it will have stack storage) and its memory will be de-allocated once execution of that method or block is […]
Continue ReadingThis is a common interview question at an early stage of your career and an important one too. So, let’s understand why we need a virtual interface in our environment. Interface signals are static ( Physically available ) in nature where the Class-based environment is dynamic in nature So, A virtual interface is a pointer […]
Continue ReadingPolymorphism is the ability to have the same code act differently based on the type of Object that its being working with. This is a key topic of any Object Oriented Programming language. SystemVerilog enables Polymorphism in two ways: Dynamic (Run-Time) Static (Compile-Time) Here we’ll discuss the Dynamic mode of Polymorphism which is supported via “Virtual […]
Continue ReadingBefore going towards Virtual and Pure Virtual methods let’s understand Virtual Class (Abstract Class) to make it more clear the understanding of exact concepts. Virtual Class (Abstract Class): Abstract class is nothing but a class that can be extended but cannot be instantiated. It’s the intention to be only a base class or prototype class. […]
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