Async FIFO Verification, Part 1: The Design, Gray Pointers and a Starter UVM Bench
Async FIFO verification, part 1: Gray-coded pointers, the full and empty flags, a verification plan and a starter UVM bench with real VCS logs.
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Assertions | Functional Coverage | Interview Questions | System Verilog | UVM | Verification Fundamentals
Clock Multiplication vs Division: Which to Use and Why
In short: Designs need many clock frequencies from one reference. Division is simple but only gives integer ratios below the reference and can pile up jitter across a long chain. Multiplication, usually via a PLL, reaches higher frequencies, supports non-integer ratios, and often has lower jitter, which is why it suits high-speed links, CPU cores,…
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Clock Monitors in SoC Verification
In short: A clock monitor is a reusable SystemVerilog/UVM component that watches a clock signal and automatically checks its frequency, duty cycle, and on-the-fly switching, and flags glitches or timeouts. Because it is built as a uvm_monitor inside a uvm_agent, you can plug it into any UVM environment and verify complex clock systems without writing…
