System Verilog rand_mode() and constraint_mode()
In short: rand_mode() turns the random nature of a variable on or off, and constraint_mode() turns a constraint block on or off, both at run time. Call obj.rand_mode(0) to freeze all random variables or obj.var.rand_mode(0) for a single one; a frozen variable keeps its current value through randomize. Call obj.constraint_mode(0) to disable all constraints or…