In short: An assertion is a small rule that describes how a design should behave. If the design breaks the rule during simulation, the assertion fails and points you straight to the problem. The big advantages are early bug detection, better visibility into what went wrong, reuse in both simulation and formal tools, and a…
In short: To enable or disable one specific constraint, call constraint_mode() on the named block, not on the whole object: obj.block_name.constraint_mode(0) switches that one rule off, and obj.block_name.constraint_mode(1) switches it back on. Every other constraint keeps working. Called with no argument on a named block it returns the current state, 1 for enabled and 0…
In short: randcase picks one branch at random using weights: each branch weight divided by the sum of all weights is its chance of being taken. randsequence is bigger; it builds structured sequences from named productions, so it can produce ordered or branching stimulus such as instruction streams. Use randcase for a quick weighted choice…
In short: Both @(e) and wait(e.triggered) pause a process until event e fires, but they treat timing differently. @(e) is edge-sensitive: the process must already be blocked on it before the trigger, or it misses the event. wait(e.triggered) is level-sensitive within the current time step: it still catches the event even if the trigger happened…
In short: A mailbox in SystemVerilog is a built in class that lets two parallel processes pass data safely, like a FIFO with a producer on one side and a consumer on the other. The producer calls put() to add an item and the consumer calls get() to take one. put() and get() block when…
In short: The dist keyword in a constraint makes some random values appear more often than others. Two operators set the weights. := gives the stated weight to each value in a range, so a wider range gets more total probability. :/ gives the stated weight to the range as a whole, split evenly across…
In short: Directed testing writes one test per scenario you already know about. Constrained random verification (CRV) lets the simulator generate many legal, varied scenarios from a small set of rules, so it also finds bugs nobody thought to look for. Most real projects use both: CRV first to cover wide ground and catch corner…
In short: SVA bind lets you attach assertions to a design module without editing that module. You write your checkers in a separate assertion module, then use the bind keyword to connect them to a target module or a specific instance. The design source stays untouched, which is ideal when you are not allowed to…
In short: A semaphore in SystemVerilog controls access to a shared resource by handing out a fixed number of keys. A process calls get() to take one or more keys before using the resource and put() to return them when done. If no key is free, get() blocks until one is returned; try_get() checks without…
In short: SystemVerilog gives you four main array types beyond the fixed size array: the dynamic array (size set at run time with new[]), the associative array (sparse, indexed by any key such as a string), the queue (an ordered list that grows and shrinks with push and pop), and each has its own methods….