In short: Plain SystemVerilog gives you the language features to build a testbench, but you build everything by hand each time. UVM (the Universal Verification Methodology, IEEE 1800.2) adds a ready-made class library and a set of rules for how to put a testbench together. The payoff is reuse, a clean split between tests and…
In short: A virtual sequence is a top-level sequence that does not drive a driver itself. Instead it starts other sequences on several real sequencers and controls their order and timing. A virtual sequencer is a sequencer with no driver that just holds handles to those real sequencers. Together they let one test coordinate traffic…
In short: A static class property is shared by every object of the class: there is one copy, not one per instance. A static method belongs to the class rather than to any object, so you call it with the class scope operator (ClassName::method()) without creating an instance, and it can only touch static members….
In short: In SystemVerilog, a variable’s lifetime decides when its memory is created and freed. A static variable is created once and lives until the simulation ends, so every call shares the same copy. An automatic variable lives on the stack: a fresh copy is made each time you enter the task, function, or block,…
In short: A virtual interface is a pointer (a handle) to a real, physical interface in SystemVerilog. Testbench classes are created and destroyed at run time (they are dynamic), while an interface with its wires is fixed at elaboration (it is static). A class cannot hold a static interface directly, so it holds a virtual…
In short: Polymorphism lets the same call run different code depending on the actual object type behind a handle. In SystemVerilog the run-time form uses virtual methods. If a base-class method is virtual, calling it through a base handle that points at a derived object runs the derived version. Once a method is virtual it…
In short: A virtual method can be overridden in a child class, and the call is resolved by the actual object type at run time, not by the handle type. That is polymorphism. A pure virtual method goes a step further: it is only a prototype with no body, declared inside a virtual (abstract) class,…
In short: The streaming operator in SystemVerilog reshapes data between a single vector and a group of values. Use >> to stream left to right and << to stream right to left. “Pack” squeezes several fields into one wide vector or byte queue, and “unpack” spreads a vector back out into fields. It is the…
In short: Inheritance lets one class (the child) reuse the fields and methods of another class (the parent) using the extends keyword. The child gets everything the parent has, can add new members, and can replace a parent method by overriding it. Mark methods virtual so the right version runs when you call through a…
In short: There are two families of coverage metrics. Code coverage is measured automatically by the simulator and tells you how much of the RTL was exercised (statement, block, branch, condition or expression, toggle, and FSM). Functional coverage is written by you and tells you whether the features from the test plan were actually tested….