Creative ways to solve problems
uvm_resource_db: uvm_resource_db is base class and uvm_config_db is extended from uvm_resource_db. Using the resource_db requires that the scope (arbitrary string) for the set and get a match. For trivial environments, this isn’t difficult. However, for complex environments, including IP from different sources, it’s more difficult to manage. That, along with some other non-intuitive behaviors of […]
Continue ReadingFork..Join: Fork…Join construct of System Verilog actually enables concurrent execution of each of its statements/threads/processes. This feature is most widely used for forking parallel processes/threads in System Verilog Test Benches. System Verilog came up with new and advanced flavors of fork join construct which adds a lot of value for implementers. Fork..Join_any Fork..Join_none Let’s start […]
Continue ReadingMultiple sequences can interact concurrently with a driver connected to a single interface. The sequencer supports an arbitration mechanism to ensure that at any point of time only one sequence has access to the driver. The choice of which sequence can send a sequence_item is dependent on a user selectable sequencer arbitration algorithm. There are […]
Continue ReadingIntroduction: It is necessary to manage most of the verification tasks, such as generating stimulus and collecting coverage data, at the transaction level, which is the natural way of verification engineers tend to think of the activity of a system. UVM provides a set of transaction-level communication interfaces and channels that you can use to […]
Continue ReadingShallow Copy: As we know that Classes contains Properties and Methods. A Class may also contain other Class Instantiation as a part of it. All these variables inside a Class got initialized once the Class is constructed. How does that happen, lets see using the following example: Here we are having two Classes named “Class […]
Continue ReadingConcept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept. The this keyword is an implicit argument to a method that refers to the current object. Let’s understand this concept with the following example. In above example we can […]
Continue ReadingThe UVM sequence-driver API majorly uses blocking methods on sequencer and driver side as explained below for transferring a sequence item from sequencer to driver and collecting response back from driver. Sequencer side operations: There are two methods as follows: start_item(<item>): This requests the sequencer to have access to the driver for the sequence item […]
Continue ReadingVariable uvm_sequence_base::starting_phase is deprecated and replaced by two new methods set_starting_phase and get_starting_phase, which prevent starting_phase from being modified in the middle of a phase. This change is not backward-compatible with UVM 1.1, though variable starting_phase, although deprecated, has not yet been removed from the base class library. New method uvm_sequence_base::set_automatic_phase_objection causes raise_objection and drop_objection […]
Continue ReadingBefore we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. A wire is a data type that can model physical wires to connect two elements and It should only be driven by continuous assignment statement and cannot hold any value if not driven. “Reg” in Verilog […]
Continue ReadingReset testing is a crucial element of functional sign-off for any chip. The architectural components of the entire verification environment need to be correctly synchronized to be made aware of the reset condition. Scoreboards, drivers and monitors need to be tidied up, and the complex stimulus generation needs to be killed gracefully. As we know, […]
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