In short: uvm_config_db and uvm_resource_db are two ways to pass settings and handles across a UVM testbench without wiring them through every constructor. uvm_config_db is the everyday choice: it stores a value against a path and a name, and a component lower down reads it back. uvm_resource_db is the lower layer underneath it, used when…
In short: A fork…join block runs its statements in parallel. The three flavours differ in when the parent thread continues: join waits for all spawned threads, join_any waits for the first one to finish, and join_none waits for none and moves on at once. Two helpers go with them: wait fork blocks until all child…
In short: When several sequences run on one sequencer at the same time, the sequencer must decide whose item goes to the driver next. That decision is arbitration. UVM offers six built-in policies, set with set_arbitration, ranging from strict round-robin to weighted and priority-based schemes. Sequences can also raise their priority, or use lock and…
In short: UVM TLM lets components talk by passing whole transactions through ports instead of wiggling signals. One component owns a port (the caller), another owns an imp that holds the real method, and connect() joins them in the environment. A uvm_analysis_port is the one-to-many version used to broadcast, for example from a monitor to…
In short: A shallow copy duplicates only the top-level fields of an object. If the object holds a handle to another object, the copy shares that same inner object, so changing it through one handle affects both. A deep copy duplicates the top-level fields and also builds fresh copies of every nested object, so the…
In short: The this keyword is a built-in handle that refers to the current object, the specific instance whose method is running. Its most common use is inside a constructor or method when a parameter has the same name as a class field: this.x = x; means “set this object’s field x to the parameter…
In short: The driver and sequencer talk through a pair of matching ports: the driver has a seq_item_port, the sequencer has a seq_item_export, and connect_phase joins them. The driver pulls one item with get_next_item, drives it onto the pins, then calls item_done to release the sequence. That get, drive, done handshake is the heartbeat of…
In short: A sequence normally has to raise an objection before it runs and drop it after, or the run phase ends too early. UVM can do this for you: call set_automatic_phase_objection(1) in the sequence, and UVM raises the objection just before the sequence starts and drops it after it finishes. It only works when…
In short: In SystemVerilog, logic is a 4-state data type (0, 1, X, Z) that replaces the old Verilog reg in most cases. It can be driven by one procedural block or one continuous assignment, so you no longer have to choose between reg and wire for single-driver signals. Use logic for almost every signal…
In short: Reset testing checks that your whole verification environment reacts correctly when reset is applied in the middle of activity. UVM makes this clean with run-time sub-phases (pre_reset, reset, post_reset, configure, main, shutdown) that run in parallel with the run phase, plus a phase jump feature. You drive traffic in the main phase, assert…