In short: Formal verification uses mathematics to prove a design property is always true, for every possible input, instead of checking a few cases with simulation. It pays off most when you apply it function by function, not block by block: pick the parts that are hard to cover in simulation, carry the most risk,…
In short: SoC verification is mostly about integration: the individual IP blocks are already verified, so at the chip level you focus on how they connect and work together. The key areas are pin muxing, protocol checks at block boundaries, reset and boot-up, memory and register access, control and data paths, analog integration, low power,…
In short: IP verification happens in seven stages, from the smallest unit up to the finished chip running real workloads: unit level, module level, SoC level, design-flow tool checks, interoperability, customer module and SoC verification, and finally customer and system-level use. Each stage catches a different class of bug, so a problem found early is…
In short: An interrupt is a sideband signal from a design block that says “something needs attention now”. In a UVM testbench you model interrupt handling by watching the interrupt lines and, when one fires, starting an interrupt service routine (ISR) sequence that uses grab() to take exclusive control of the sequencer. The ISR clears…
In short: A clock monitor is a reusable SystemVerilog/UVM component that watches a clock signal and automatically checks its frequency, duty cycle, and on-the-fly switching, and flags glitches or timeouts. Because it is built as a uvm_monitor inside a uvm_agent, you can plug it into any UVM environment and verify complex clock systems without writing…
In short: AXI (Advanced eXtensible Interface) is Arm’s on-chip bus for connecting masters like CPUs and DMA engines to memories and peripherals. It splits every transfer into five independent channels: write address, write data, write response, read address and read data. Each channel moves a beat only when VALID and READY are both high. Bursts…
In short: This is part two of building a full UVM environment for the pipe design. Here we finish the driver so it actually wiggles the pins, add the sequencer, and write several sequences: a single packet, many packets, and a directed case. We also explain the handshake between a sequence and the driver, so…
In short: This is part one of a four part series where we build a full UVM environment, step by step, to verify a small design. In this part we study the design under test (a two channel pipe), write its SystemVerilog interface, and create the transaction (the data packet) that will carry stimulus and…
62 UVM interview questions and answers with working code, grouped from basics to debug and scenario rounds, plus a small testbench to build and AI prompts to practice with. Updated for 2026.
In short: These SystemVerilog interview questions are grouped by topic and answered with real, worked code you can run. They cover data types, arrays, classes and OOP, randomization and constraints, threads and events, interfaces and clocking blocks, plus verification metrics. Each answer explains the why, not just the what, so you can defend it in…
