The Practical Verification Debug Guide: A Repeatable Method (+ AI-Assisted Debug)
A repeatable verification debug method: the five-door order, UVM and SystemVerilog tips, waveform tracing, regression triage, and an AI-assisted debug flow.
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From RTL to Reality: Inside Hardik Trivedi’s Design Verification Journey
In the fast-moving business of chip design, where logic and silicon come together to power the devices we rely on every day, a group of quiet problem solvers does the careful work behind the scenes: ASIC verification engineers. These are the people who chase down bugs before a chip ever reaches production, testing every path…
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Assertions | Functional Coverage | Interview Questions | System Verilog | UVM | Verification Fundamentals
Clock Multiplication vs Division: Which to Use and Why
In short: Designs need many clock frequencies from one reference. Division is simple but only gives integer ratios below the reference and can pile up jitter across a long chain. Multiplication, usually via a PLL, reaches higher frequencies, supports non-integer ratios, and often has lower jitter, which is why it suits high-speed links, CPU cores,…
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Formal Verification vs Functional Verification: A Tale of Two Approaches
In short: Formal and functional verification are partners. Formal uses mathematics to prove a property holds for every possible case, which fits small control logic and safety-critical corners. Functional runs simulations across many realistic scenarios and scales to a full system, but it can only sample the state space. Strong teams use formal for the…
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How to Build a Strong Verification Plan
In short: A verification plan is the map for the whole effort. It lists every feature to check, ranks them by risk, matches each to the right stimulus and technique, and ties coverage goals and a schedule to them so problems appear early. Read the spec first, blend random, directed, and environment-driven stimulus, track coverage…
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Why Debugging Is More Art Than Science
In short: Debugging carries a scientific name, but the toughest failures are cracked by judgment, not formulas. You follow clues like a detective, lean on experience to sense where a bug hides, invent unplanned stress cases, and talk the problem through with your team. The rigorous side confirms a cause; the artistic side is what…
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The Thought Process Behind Great Verification
In short: Good verification is less about tools and more about how you think. Five habits carry most of the weight: thinking strategically about the whole system, reading the design the way its author did, inventing test cases that push past the happy path, choosing the right method for each job, and sharing what you…
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Why Stress Verification Matters in UVM
In short: Coverage-driven verification checks that the planned behavior works. Stress verification pushes the design past its comfort zone with heavy, back-to-back, and unexpected traffic to see where it bends or breaks. It finds corner cases and bottlenecks that ordinary tests miss, so the chip holds up in the messy real world, not just in…
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How to approach solving complex issues?
In short: A hard bug is easier when you work in order instead of guessing. Reproduce it reliably, break the flow into small parts, gather logs and waveforms, read the data for patterns, then find the root cause before you change anything. Fix one thing at a time, ask for a second pair of eyes…
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How to Verify Complex RISC-V–based Designs?
In short: Verifying a RISC-V design has two parts: prove the core is correct and ISA compliant, and prove the whole system built around it works. As the system grows with more cores, peripherals, and custom hardware, RTL simulation alone gets too slow. Transaction-level hardware emulation (ideally on the Accellera SCE-MI standard), with an ISS…
