Interview Preparation

Real questions verification interviews ask, with answers that explain the reasoning, not just the result. Start with a question set, then revise the subjects below.

Question sets

15 min readSystem Verilog Interview Questions38 min readUVM Interview Questions

Beginner

11 min readHow to think like a Verification Engineer5 min readThe Thought Process Behind Great Verification

Intermediate

7 min readGeneral Questions on Coverage9 min readDifferent Stages of IP Verification5 min readHow to Build a Strong Verification Plan5 min readClock Multiplication vs Division: Which to Use and Why

Advanced

32 min readUnderstanding with AXI Protocol and Cache Coherency24 min readAI IN VERIFICATION | METHODOLOGY17 min readThe Practical Verification Debug Guide: A Repeatable Method (+ AI-Assisted Debug)32 min readPortable Stimulus (PSS) Guide 2026: Working Examples and How AI Helps

More interview reading

3 min readFrom RTL to Reality: Inside Hardik Trivedi’s Design Verification Journey

Revise by subject

SystemVerilog for verification 28UVM methodology 26Assertions (SVA) 5Functional coverage 4Verification fundamentals 8
Debugging Methodology 3Formal Verification 2Protocols: AXI 1SoC Verification 5

A four-week plan

Most verification interviews test the same four things, in roughly this order. Give each one a week. Finish every week by answering the questions out loud, as if someone were sitting across the table.

  1. Week 1. SystemVerilog. Data types, classes, inheritance, polymorphism and randomization. Work through stages 1 to 3 of the SystemVerilog learning path, then the SystemVerilog question set.
  2. Week 2. UVM. Testbench architecture, factory, config_db, sequences and phasing. Stages 1 to 4 of the UVM learning path, then the UVM question set.
  3. Week 3. Assertions and coverage. The Assertions path and the Functional coverage path. Be ready to write a small property and a covergroup by hand.
  4. Week 4. Thinking and debugging. The Verification fundamentals path and the scenarios below. For experienced roles, expect more questions about how you reason than about syntax.

Scenario questions to practise

These are the questions that separate a memorised answer from real experience. Try each one before you open the linked article.

  1. Your regression passes, but functional coverage has stopped climbing. What do you look at first? Read first: Functional Coverage Guidelines for Implementers
  2. A test fails with one seed and passes with every other. How do you find the cause? Read first: The Practical Verification Debug Guide
  3. The driver gets the first item from the sequencer, then everything hangs. Where is the bug likely to be? Read first: UVM Sequencer and Driver Communication
  4. Your test ends before the design finishes its last transfer. Why, and how do you fix it? Read first: How to Terminate UVM Test? (UVM Objections)
  5. You need to apply a reset in the middle of a running test and check that the design recovers. How would you build it? Read first: Reset Testing using Phase Jump in UVM
  6. Write a check that every request gets a grant within four clock cycles. Read first: Basic Assertions Examples Part-1
  7. Traffic on two interfaces has to happen in a fixed order. How do you coordinate the two agents? Read first: Virtual Sequence and Sequencers
  8. When would you choose formal verification over simulation for a block? Read first: Formal Verification: Where to use it and Why?

In the interview room

  • Think out loud. The interviewer is scoring how you reach the answer as much as the answer itself.
  • Before you answer a debug question, say what you would check first and why.
  • Draw the testbench. A quick sketch of agents, sequencer, driver, monitor and scoreboard makes every UVM answer clearer.
  • If you don’t know, say how you would find out. That is what the job is every day.