You already know what a covergroup is. This page skips the basics. It points you at the parts of the site written for engineers who debug, review and sign off real testbenches: experiments with real simulator logs, debug playbooks, methodology and protocol depth.
Experiments with real results
Every result here comes from code that ran on a real simulator. The prompts, benches and logs are published so you can repeat them.
- I Gave AI a UVM Spec: It Caught 4 of 4 Bugs. Our Hand-Written Bench Caught 2: one prompt, four hidden bugs, real VCS logs, and every file to download
- AI in ASIC Verification: A Practical Method (With Limits): where AI helps today, where it fails, and the guardrails that keep it honest
Debug playbooks
- UVM Scoreboard Mismatch: How to Find the Real Cause: six causes, a 5-minute triage and five planted bugs to practise on
- The Practical Verification Debug Guide: A Repeatable Method (+ AI-Assisted Debug): a repeatable method for any failing test, with a log-bucketing script
Methodology and architecture
- SoC Verification Flow: Step-by-Step From IP to Silicon: IP to post-silicon, with an exit gate and typical bugs for each level
- UVM Testbench Architecture (2026): Diagram, Components, Example: the reference layout, run on VCS, including a broken-DUT check
- Portable Stimulus (PSS) Guide 2026: Working Examples and How AI Helps: when Portable Stimulus earns its place next to SystemVerilog sequences
- Formal Verification vs Functional Verification: A Tale of Two Approaches: what each approach proves and where each one runs out
- How to Build a Strong Verification Plan: turning a spec into features, checks and coverage you can sign off
Protocol depth
- AXI Protocol Verification in 2026: SystemVerilog and UVM Guide: channels, IDs, bursts and the checks a UVM environment needs
- AXI Protocol Explained: Channels, Handshake, Bursts and Cache Coherency: handshake, burst and coherency details with tested examples
Advanced UVM
- Virtual Sequence and Sequencers: coordinating several agents from one place
- Reset Testing using Phase Jump in UVM: repeating reset mid-test with phase jumps
- Callbacks Vs Factory: which extension mechanism to reach for, and why
- UVM Sequence Arbitration Mechanism: how the sequencer picks between competing sequences
- uvm_report_catcher/uvm_error demoter Example: demoting known errors without hiding new ones
Coming next
A coverage closure method, constrained-random debugging, CDC, and two complete projects (a FIFO and an APB UVM environment), each with code that runs. Get them first in The Verification Engineer’s Brief, one useful verification idea at a time.