In short: A hard bug is easier when you work in order instead of guessing. Reproduce it reliably, break the flow into small parts, gather logs and waveforms, read the data for patterns, then find the root cause before you change anything. Fix one thing at a time, ask for a second pair of eyes…
In short: Verifying a RISC-V design has two parts: prove the core is correct and ISA compliant, and prove the whole system built around it works. As the system grows with more cores, peripherals, and custom hardware, RTL simulation alone gets too slow. Transaction-level hardware emulation (ideally on the Accellera SCE-MI standard), with an ISS…
In short: Formal verification uses mathematics to prove a design property is always true, for every possible input, instead of checking a few cases with simulation. It pays off most when you apply it function by function, not block by block: pick the parts that are hard to cover in simulation, carry the most risk,…
In short: SoC verification is mostly about integration: the individual IP blocks are already verified, so at the chip level you focus on how they connect and work together. The key areas are pin muxing, protocol checks at block boundaries, reset and boot-up, memory and register access, control and data paths, analog integration, low power,…
In short: IP verification happens in seven stages, from the smallest unit up to the finished chip running real workloads: unit level, module level, SoC level, design-flow tool checks, interoperability, customer module and SoC verification, and finally customer and system-level use. Each stage catches a different class of bug, so a problem found early is…
In short: An interrupt is a sideband signal from a design block that says “something needs attention now”. In a UVM testbench you model interrupt handling by watching the interrupt lines and, when one fires, starting an interrupt service routine (ISR) sequence that uses grab() to take exclusive control of the sequencer. The ISR clears…
In short: A virtual interface is a handle that lets your class-based UVM code reach a real, static interface connected to the DUT. You pass it in with uvm_config_db#(virtual my_if)::set from the top module, then each component reads it with get in build_phase. This keeps the run-time class world and the static module world connected…
In short: A clock monitor is a reusable SystemVerilog/UVM component that watches a clock signal and automatically checks its frequency, duty cycle, and on-the-fly switching, and flags glitches or timeouts. Because it is built as a uvm_monitor inside a uvm_agent, you can plug it into any UVM environment and verify complex clock systems without writing…
In short: UVM RAL (Register Abstraction Layer) is a labelled remote control for the registers inside your chip. Your test reads and writes registers by name, like regmodel.uart.baud_div.write(…), and RAL turns each call into the correct bus activity. It also keeps a mirror copy of every register so your checks always know the expected value….
In short: AXI (Advanced eXtensible Interface) is an on-chip bus from the AMBA family that moves data using five independent channels, address-first bursts, and a simple valid/ready handshake. Cache coherency keeps every cached copy of a memory address in agreement. This guide answers the AXI protocol and cache coherency interview questions the way an interviewer…
