UVM methodology

Stage 1 · Foundations and testbench structure

1 Advantages of UVM over SV9 min read Beginner 2 Typical UVM Testbench Architecture14 min read Beginner 3 How to build UVM Environment Part – 19 min read Beginner 4 How to build UVM Environment Part – 28 min read Beginner 5 How to Build UVM Environment Part – 37 min read Beginner 6 How to Build UVM Environment Part – 47 min read Beginner

Stage 2 · Factory and configuration

7 Concept of UVM Factory8 min read Intermediate 8 Create() Vs new()7 min read Intermediate 9 uvm_config_db and uvm_resource_db7 min read Intermediate 10 How Virtual Interface can be pass using uvm_config_db in the UVM Environment?5 min read Intermediate

Stage 3 · Communication and stimulus

11 UVM TLM Concepts10 min read Intermediate 12 UVM Sequencer and Driver Communication9 min read Intermediate 13 M_sequencer Vs P_sequencer6 min read Intermediate 14 Virtual Sequence and Sequencers11 min read Intermediate 15 UVM Sequence Arbitration Mechanism6 min read Intermediate

Stage 4 · Phasing and ending a test

16 UVM Phasing9 min read Intermediate 17 How UVM Phasing is triggered?6 min read Intermediate 18 How to Terminate UVM Test? (UVM Objections)6 min read Intermediate 19 Raise/Drop objection Automatically with UVM8 min read Intermediate

Stage 5 · Reporting and callbacks

20 UVM Macros, Messaging and UVM Reporting8 min read Intermediate 21 uvm_report_catcher/uvm_error demoter Example6 min read Intermediate 22 How UVM Callback works?8 min read Advanced 23 Callbacks Vs Factory6 min read Advanced

Stage 6 · Advanced UVM

24 How UVM RAL works?12 min read Advanced 25 Reset Testing using Phase Jump in UVM17 min read Advanced 26 How to handle Interrupt in UVM?8 min read Advanced