Immediate assertions use expressions and are executed like a statement in a procedural block. They are not temporal in nature and are evaluated immediately when executed. Immediate assertions are used only in dynamic simulations. Following is an example of a simple immediate assertion that checks “if x and y are always equal”: Concurrent assertions are temporal…
Nowadays in many verification scenarios, it requires to create a set of random instructions or addresses with each unique value or we can say that no repeating values, usually represented as elements in a dynamic array. Earlier versions of SystemVerilog required you to use either nested foreach loops to constraint all combinations of array elements…
Without using Random variable and constraint, you can generate array of random unique values using below code, but it is not fully random.
rand_mode(): Variables who is having random nature declared as rand or randc can be turned on or off dynamically by using an in-built method called rand_mode(). It can be called either function or task. In the below example, you can see that how rand_mode we are going to use to disabled and enabled all variables….
An assertion is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening in the design and occurs during simulation, then also the assertion fails. Following…
In below example we can understand how we can enable or disable a specific constraint whenever we need to do.
Randcase: Randcase is a case statement that randomly selects one of its branches just like a case statement in Verilog but here as its randcase so it will pick statements randomly. Randcase can be used in class or modules. The randcase item expressions are non-negative integral values that constitute the branch weights. An item weight…
SystemVerilog supports two ways through which we can wait for a particular event to be triggered. So let’s understand what is the exact difference between those two ways of event trigger with the following example. An event trigger ->e is an instantaneous event. The event control @e has to execute and block the current process…
While learning System Verilog you always thought like How do you pass information between two threads/processes? The solution is a SystemVerilog mailbox. From a hardware point of view, the easiest way to think about a mailbox is that it is just a FIFO, with a source and sink. The source puts data into the mailbox,…
In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage. To resolve this issue you can use…