Assertions and Advantages of Assertions

ByThe Art of Verification March 24, 2021September 15, 2021

An assertion is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening in the design and occurs during simulation, then also the assertion fails.

Following are some of the advantages of using Assertions in Verification:

Assertions improve error detection in terms of catching simulation errors as soon a design specification is violated
Assertions provide better observability into the design and hence help in easier debug of test failures.
Assertions can be used for both dynamic simulations as well as in formal verification of design
Assertions can also be used to provide functional coverage on input stimulus and to validate that a design property is in fact simulated

System Verilog

Mailbox in System Verilog

ByThe Art of Verification March 24, 2021September 15, 2021

While learning System Verilog you always thought like How do you pass information between two threads/processes? The solution is a SystemVerilog mailbox. From a hardware point of view, the easiest way to think about a mailbox is that it is just a FIFO, with a source and sink. The source puts data into the mailbox,…

UVM

How to handle Interrupt in UVM?

ByThe Art of Verification September 4, 2021April 7, 2023

Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many IP blocks as part of it. In some way or other Interrupts are used to act as the sideband signals of the Design/IP Blocks & most of the time it’s not the part of the main…

System Verilog

Concept of “This” in System Verilog:

ByThe Art of Verification March 24, 2021April 23, 2021

Concept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept. The this keyword is an implicit argument to a method that refers to the current object. Let’s understand this concept with the following example. In above example we can…

Assertions

System Verilog Assertion Binding (SVA Bind)

ByThe Art of Verification March 24, 2021August 17, 2023

Nowadays we use to deal with modules of Verilog or VHDL or a combination of both. Mostly verification engineers are not allowed to modify these modules. But still, SVA addition to these modules is required, and easy to verify a lot of RTL functionality. How can you add SVA to these modules? Let’s find out…

System Verilog

Polymorphism:

ByThe Art of Verification March 24, 2021September 15, 2021

Polymorphism is the ability to have the same code act differently based on the type of Object that its being working with. This is a key topic of any Object Oriented Programming language. SystemVerilog enables Polymorphism in two ways: Dynamic (Run-Time) Static (Compile-Time) Here we’ll discuss the Dynamic mode of Polymorphism which is supported via “Virtual…

System Verilog | UVM

Clock Monitors in SoC Verification

ByThe Art of Verification August 5, 2021April 7, 2023

Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors that use new bus architectures to communicate with them. They can also have various interfaces like I2C, PCM, I2S, AHB, etc. Yet, these SoC components will share a single clock control unit. This module generates…

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