Why do we need a Virtual Interface?

ByThe Art of Verification March 24, 2021September 15, 2021

This is a common interview question at an early stage of your career and an important one too. So, let’s understand why we need a virtual interface in our environment. Interface signals are static ( Physically available ) in nature where the Class-based environment is dynamic in nature So, A virtual interface is a pointer to an actual interface in SystemVerilog. It is most often used in classes to provide a connection point to allow classes to access the signals in the interface through the virtual interface pointer dynamically

UVM

How UVM Phasing is triggered?

ByThe Art of Verification March 24, 2021April 23, 2021

To start a UVM Testbench, the run_test() method has to be called from the static part of the Testbench i.e called from an initial block in the top module of the Testbench. Once the run_test() method is called, it constructs the root component of the UVM environment & then triggers the UVM Phasing process. The…

Interview Questions

UVM Interview Questions

ByThe Art of Verification March 25, 2021April 7, 2023

If you’re looking to enter the world of ASIC or FPGA verification, then chances are you’ve heard of Universal Verification Methodology (UVM). UVM has become the industry standard for verifying digital designs, and as such, it is a crucial skill set for anyone looking to break into the field. Whether you’re a recent graduate or…

System Verilog

Logic in Systemverilog:

ByThe Art of Verification March 24, 2021April 23, 2021

Before we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. A wire is a data type that can model physical wires to connect two elements and It should only be driven by continuous assignment statement and cannot hold any value if not driven. “Reg” in Verilog…

UVM

How to build UVM Environment Part – 1

ByThe Art of Verification May 16, 2021May 16, 2021

In earlier post i.e. https://theartofverification.com/uvm-testbench-architecture/ we learned which all components are required to develop UVM Environment/Testbench to verify complex Designs. In this blog post we will verify a small RTL Design by developing complete UVM Environment. Let’s start with the basic RTL Design and understand it’s specifications/working. Here as we can see that in the…

System Verilog

Polymorphism:

ByThe Art of Verification March 24, 2021September 15, 2021

Polymorphism is the ability to have the same code act differently based on the type of Object that its being working with. This is a key topic of any Object Oriented Programming language. SystemVerilog enables Polymorphism in two ways: Dynamic (Run-Time) Static (Compile-Time) Here we’ll discuss the Dynamic mode of Polymorphism which is supported via “Virtual…

Assertions

Assertions and Advantages of Assertions

ByThe Art of Verification March 24, 2021September 15, 2021

An assertion is used to validate the behavior of the design. If the property that is being checked for in a simulation does not behave as per specification, then the assertion fails. Similarly if a property or rule is forbidden from happening in the design and occurs during simulation, then also the assertion fails. Following…

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