UVM

Callbacks Vs Factory

ByThe Art of Verification March 24, 2021April 6, 2021

Callbacks and factory both addresses different areas of reusability in UVM.

Callback:

Add functionality to existing logic.
Suitable for rare or minimal feature need to be enhanced in focus
Popular for error injection/to corrupt the sequence from VIP.
Easy to maintain callbacks

Factory:

It used to substitute the existing component before build, keeps environment same.
Suitable for so many features need to be enhanced in focus.
Multiple copies are required
Not suitable for VIP components

As the callback and factory can be interchangeably used to address the same problem. Depending on the requirement, a wise decision should be made on which feature the user should use.

System Verilog

Constraint Override in System Verilog:

ByThe Art of Verification March 24, 2021September 15, 2021

Here in this overriding of constraint if we will have the same constraint name in the parent class as well as child class then we can say that our constraint is overridden in the child class. Let us understand through an example: In the above example, you can observe that the EDA tool will try…

UVM

How to Build UVM Environment Part – 4

ByThe Art of Verification May 16, 2021May 16, 2021

Scoreboard The basic function of the scoreboard is to check the correctness of the output data of the design under test. The scoreboard you create should derive from uvm_scoreboard; however, there is no current functionality of the uvm_scoreboard. You may be wondering why it’s important to mention if it doesn’t have any functionality at the…

UVM

How UVM Phasing is triggered?

ByThe Art of Verification March 24, 2021April 23, 2021

To start a UVM Testbench, the run_test() method has to be called from the static part of the Testbench i.e called from an initial block in the top module of the Testbench. Once the run_test() method is called, it constructs the root component of the UVM environment & then triggers the UVM Phasing process. The…

UVM

Advantages of UVM over SV

ByThe Art of Verification March 24, 2021April 23, 2021

UVM is a standard verification methodology which is getting standardized as IEEE 1800.12 standard. UVM consists of a defined methodology in terms of architecting testbenches and test cases, and also comes with a library of classes that helps in building efficient constrained random testbenches easily. Some of the advantages are listed below: Modularity and Reusability:…

System Verilog

How to generate an array of unique random values

ByThe Art of Verification March 24, 2021September 15, 2021

Nowadays in many verification scenarios, it requires to create a set of random instructions or addresses with each unique value or we can say that no repeating values, usually represented as elements in a dynamic array. Earlier versions of SystemVerilog required you to use either nested foreach loops to constraint all combinations of array elements…

System Verilog

Directed Testing Vs Constraint Random Verification

ByThe Art of Verification March 24, 2021September 15, 2021

Directed Verification Technique with a set of directed tests is extremely time-consuming and difficult to maintain for more complex designs to verify. Directed tests only cover scenarios that have been anticipated by the verification team by going through specifications, This can lead to costly re-spins and still, there are chances of missing time to market…

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