UVM

Callbacks Vs Factory

ByThe Art of Verification March 24, 2021April 6, 2021

Callbacks and factory both addresses different areas of reusability in UVM.

Callback:

Add functionality to existing logic.
Suitable for rare or minimal feature need to be enhanced in focus
Popular for error injection/to corrupt the sequence from VIP.
Easy to maintain callbacks

Factory:

It used to substitute the existing component before build, keeps environment same.
Suitable for so many features need to be enhanced in focus.
Multiple copies are required
Not suitable for VIP components

As the callback and factory can be interchangeably used to address the same problem. Depending on the requirement, a wise decision should be made on which feature the user should use.

Interview Questions

Understanding with AXI Protocol and Cache Coherency

ByThe Art of Verification June 24, 2021October 5, 2021

As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so knowledge of those concepts are must for everyone to know how it works. All AXI and Cache Coherency concepts are guided by one of the most experienced Verification Engineer in the industry Mr. Rahul Bhardwaj…

UVM

M_sequencer Vs P_sequencer

ByThe Art of Verification March 24, 2021April 12, 2021

M_sequencer: When a sequence is started, it is always associated with a sequencer on which it is started. The m_sequencer handle contains the reference to the sequencer on which sequence is running. Using this handle, the sequence can access any information and other resource handles in the UVM component hierarchy. P_sequencer and how it is…

UVM

How to Verify Complex RISC-V–based Designs?

ByThe Art of Verification September 23, 2022April 7, 2023

As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or around it. Understandably, verification is just as complex and time-consuming as it is for, say, an Arm processor-based project. To…

Assertions

Basic Assertions Examples Part-1

ByThe Art of Verification April 17, 2021April 17, 2021

System Verilog assertions always help to speed up the verification process and it’s very powerful and widely used in the ASIC verification. Identifying the right set of checkers in the verification plan and implementing them using effective SV assertions helps to quickly catch the design bugs and ultimately helps in high-quality design. With the ever-increasing…

System Verilog | UVM

Key Areas to consider during SOC Verification

ByThe Art of Verification January 12, 2022April 7, 2023

Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two years. The chip makers want to pack as many functions as possible in their SoCs and provide as many feature additions to…

System Verilog

Encapsulation:

ByThe Art of Verification March 24, 2021September 15, 2021

Many times we might use the Base Class or Base Class library provided by third party sources. By default, These Class Members are Public in nature. It means these Class Members can be accessed directly from outside of that Class. But sometimes Base Class providers may restrict how others can access the Class members as…

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