In the ever-evolving world of chip design, where circuits dance with logic and transistors tango with electrons, stands a breed of unsung heroes: the ASIC verification engineers. These digital detectives, armed with their arsenal of tests, hunt down bugs with the zeal of Indiana Jones and the precision of a Swiss watchmaker. Today, we delve…
In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an alternative method involves using a multiplied version of the reference clock. This blog post delves into the intricacies of handling clock…
As an experienced ASIC verification engineer, I’ve seen firsthand the importance of a thorough verification plan. A well-crafted verification plan can help to ensure that your design is bug-free and ready for production, while a poorly-crafted plan can lead to missed deadlines, costly rework, and even product recalls. In this blog post, I’ll discuss the…
Introduction Hey there, fellow ASIC Verification enthusiasts! Welcome to our deep dive into the fascinating world of verification excellence. Ever wondered what’s at the heart of it all? It’s our thought process. Yes, that’s right! Our ability to think strategically, creatively, and methodically is what sets us apart. It’s the engine that drives our work,…
The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs. Quality is even more critical for highly configurable types of IP because customers license it specifically to address the unique requirements of their systems and markets. The on-chip interconnect fabric is perhaps the…
As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so knowledge of those concepts are must for everyone to know how it works. All AXI and Cache Coherency concepts are guided by one of the most experienced Verification Engineer in the industry Mr. Rahul Bhardwaj…
1. What is the difference between code coverage and functional coverage? There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification process. 1) Code Coverage: Code coverage is a metric used to measure the degree to which the design code (HDL model) is tested by…
A verification Engineer is not just to write some test scenarios to verify something it’s way beyond that. A verification engineer’s focus after understanding specifications such as test planning, and strategy need to be applied to verify the complex design, and what needs to be implemented using which methodology. Verification engineers always emphasize why and…
If you’re looking to enter the world of ASIC or FPGA verification, then chances are you’ve heard of Universal Verification Methodology (UVM). UVM has become the industry standard for verifying digital designs, and as such, it is a crucial skill set for anyone looking to break into the field. Whether you’re a recent graduate or…
SystemVerilog is a hardware description and verification language that extends the capabilities of Verilog HDL. It is widely used in the semiconductor industry for the design and verification of digital circuits and systems. If you are preparing for a SystemVerilog interview, you may be asked a variety of questions related to the language, its features,…