How Virtual Interface can be pass using uvm_config_db in the UVM Environment?

How Virtual Interface can be pass using uvm_config_db in the UVM Environment?

How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form of signals/wire/nets at all levels in the DUT as well as in TestBench. But this is not the case in the latest “Constrained Random Verification Methodology” like…

Clock Monitors in SoC Verification
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Clock Monitors in SoC Verification

Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors that use new bus architectures to communicate with them. They can also have various interfaces like I2C, PCM, I2S, AHB, etc. Yet, these SoC components will share a single clock control unit. This module generates…

How UVM RAL works?

How UVM RAL works?

Today, let’s delve into UVM RAL: What it is, its importance, and the structure it entails. The discussion will cover the definition of RAL, the reasons for its necessity, and an overview of the UVM RAL framework design. It is essential to understand that our Device Under Test (DUT), whether an SoC or Subsystem, contains…

Mastering the SOC Verification Flow: A Comprehensive Guide
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Mastering the SOC Verification Flow: A Comprehensive Guide

In the intricate world of ASIC Verification, the SOC Verification Flow is a cornerstone process that necessitates both expertise and experience. Many people may not fully understand what sets a system-on-chip (SoC) apart from other semiconductor devices. Within the realm of electronic design automation (EDA), the term “SoC” is often used without a clear definition or explanation…

How to Build UVM Environment Part – 4

Scoreboard The basic function of the scoreboard is to check the correctness of the output data of the design under test. The scoreboard you create should derive from uvm_scoreboard; however, there is no current functionality of the uvm_scoreboard. You may be wondering why it’s important to mention if it doesn’t have any functionality at the…

How to build UVM Environment Part – 1

In earlier post i.e. https://theartofverification.com/uvm-testbench-architecture/ we learned which all components are required to develop UVM Environment/Testbench to verify complex Designs. In this blog post we will verify a small RTL Design by developing complete UVM Environment. Let’s start with the basic RTL Design and understand it’s specifications/working. Here as we can see that in the…