Constraint Override in System Verilog:
Here in this overriding of constraint if we will have the same constraint name in the parent class as well as child class then we can say that our constraint is overridden in the child class.
Let us understand through an example:
class parent;
rand int data;
constraint ct_c
{
data inside {[100:200]};
}
endclass : parent
class child extends parent;
constraint ct_c
{
data inside {[250:500]};
}
endclass : child
program main;
child c;
initial begin
c = new();
if (!c.randomize()) begin
$display("Randomization failed");
end
else begin
$display("data = %0d", c.data);
end
end
endprogram : main
In the above example, you can observe that the EDA tool will try to solve only child (extended/derived) class’s constraint because Child class Override parent class’s Constraint as both constraints is having the same name.
Let us see another example with a different constraint name:
class parent;
rand int data;
constraint ct_c
{
data inside {[100:200]};
}
endclass : parent
class child extends parent;
constraint ct_child
{
data inside {[250:500]};
}
endclass : child
program main;
child c;
initial begin
c = new();
if (!c.randomize()) begin
$display("Randomization failed");
end
else begin
$display("data = %0d", c.data);
end
end
endprogram : main
In the above example, EDA Tool will consider two different constraints so it will try to resolve both constraints because the Same variable is constrained using two different constraints (Names are different so the Child class can’t override the Parent class’s constraint) having different names and both constraints are contradict to each other.
