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System Verilog
Static Properties & Methods in SystemVerilog: A Comprehensive Guide
@event Vs wait(event.triggered) in SystemVerilog
Concept of “This” in System Verilog:
Constraint Override in System Verilog:
Different Array Types and Queues in System Verilog
Directed Testing Vs Constraint Random Verification
Enable/Disable specific constraints:
Inheritance in SystemVerilog OOPs:
Encapsulation:
Polymorphism:
Flavours of Fork..Join
Generate randc behavior from rand variable:
Generate the array of unique values without using random and constraints
How to generate an array of unique random values
Ifdef Vs plusargs:
Logic in Systemverilog:
Mailbox in System Verilog
Plusargs in SystemVerilog:
Randcase Vs Randsequence in Systemverilog
randomize() Vs std::randomize()
Semaphore in SystemVerilog:
Shallow Copy Vs Deep Copy
STATIC and AUTOMATIC Lifetime:
Streaming Operator in SystemVerilog(Pack/Unpack):
System Verilog rand_mode() and constraint_mode()
Virtual Vs Pure Virtual Methods:
Weighted Distribution in System Verilog
UVM
Advantages of UVM over SV
Callbacks Vs Factory
Clock Monitors in SoC Verification
Mastering the SOC Verification Flow: A Comprehensive Guide
Concept of UVM Factory
Create() Vs new()
Typical UVM Testbench Architecture
How to build UVM Environment Part – 1
How to build UVM Environment Part – 2
How to Build UVM Environment Part – 3
How to Build UVM Environment Part – 4
How to Terminate UVM Test? (UVM Objections)
How to handle Interrupt in UVM?
How UVM Callback works?
How UVM Phasing is triggered?
How UVM RAL works?
How Virtual Interface can be pass using uvm_config_db in the UVM Environment?
M_sequencer Vs P_sequencer
Raise/Drop objection Automatically with UVM
Reset Testing using Phase Jump in UVM
UVM Macros, Messaging and UVM Reporting:
UVM Phasing
UVM Sequence Arbitration Mechanism
UVM Sequencer and Driver Communication:
UVM TLM Concepts:
uvm_config_db and uvm_resource_db
uvm_report_catcher/uvm_error demoter Example
Virtual Sequence and Sequencers:
Why do we need a Virtual Interface?
Functional Coverage
Types of Coverage Metrics
Functional Coverage Guidelines for Implementers:
Functional Coverage Options in System Verilog
Assertions
Assertions and Advantages of Assertions
Immediate Vs Concurrent Assertions
Basic Assertions Examples Part-1
Basic Assertions Examples Part-2
System Verilog Assertion Binding (SVA Bind)
Interview Questions
System Verilog Interview Questions
UVM Interview Questions
Understanding with AXI Protocol and Cache Coherency
General Questions on Coverage:
How to think like a Verification Engineer
Books
Contact
Functional Coverage