In short: A clock monitor is a reusable SystemVerilog/UVM component that watches a clock signal and automatically checks its frequency, duty cycle, and on-the-fly switching, and flags glitches or timeouts. Because it is built as a uvm_monitor inside a uvm_agent, you can plug it into any UVM environment and verify complex clock systems without writing…
In short: This is the final part of building a UVM environment for the pipe design. Here we add the test, pass the real interface down to every component through the configuration database, add a coverage collector, build the top module that ties the design to the testbench, and finally run the first simulation. By…
In short: This is part three of building a UVM environment for the pipe design. Here we add the monitor that watches the pins, wrap the driver, sequencer, and monitor into an agent, and build a scoreboard that checks the results against a small reference model. We then group everything into an environment. After this…