Randcase: Randcase is a case statement that randomly selects one of its branches just like a case statement in Verilog but here as its randcase so it will pick statements randomly. Randcase can be used in class or modules. The randcase item expressions are non-negative integral values that constitute the branch weights. An item weight…
SystemVerilog supports two ways through which we can wait for a particular event to be triggered. So let’s understand what is the exact difference between those two ways of event trigger with the following example. An event trigger ->e is an instantaneous event. The event control @e has to execute and block the current process…
In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage. To resolve this issue you can use…
Directed Verification Technique with a set of directed tests is extremely time-consuming and difficult to maintain for more complex designs to verify. Directed tests only cover scenarios that have been anticipated by the verification team by going through specifications, This can lead to costly re-spins and still, there are chances of missing time to market…