Sequence Archives | The Art Of Verification

UVM

UVM Sequence Arbitration Mechanism

ByThe Art of Verification March 24, 2021April 23, 2021

Multiple sequences can interact concurrently with a driver connected to a single interface. The sequencer supports an arbitration mechanism to ensure that at any point of time only one sequence has access to the driver. The choice of which sequence can send a sequence_item is dependent on a user selectable sequencer arbitration algorithm. There are…

UVM

Virtual Sequence and Sequencers:

ByThe Art of Verification March 24, 2021April 23, 2021

Today I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively? Most UVM testbenches are composed of reusable verification components unless we are working on block-level verification of a simple protocol like MIPI-CSI….