In short: The difference between ifdef and plusargs is when they act. An ifdef is a compile time macro: it decides which code is built into the image, so changing it needs a recompile, but the excluded code is truly gone. A plusarg is a run time switch: the whole design is compiled once and…
In short: A constraint override happens when a child class declares a constraint with the same name as one in its parent. The child version replaces the parent version, so the solver uses only the child rule. If instead the child uses a different name, both constraints stay active and must be satisfied together, and…
In short: The class method randomize() assigns random values to the rand and randc members of an object, using that class’s constraints. The scope function std::randomize() does the same job but for plain variables in the current scope, with no class needed. Use randomize() when your random data lives in a class with reusable constraints;…
In short: Functional coverage options in SystemVerilog tune how a covergroup collects and reports data. The everyday ones are option.comment to label a group, option.per_instance to report each instance separately, option.at_least to set how many hits a bin needs, option.cross_num_print_missing to show empty bins, and option.goal to set the target percentage. They change reporting, not…
In short: A randc variable walks through every value in its range once before any value repeats. You can copy that no repeat behaviour with a plain rand variable by keeping a list of values already produced and adding a constraint that excludes them. In post_randomize() you push the new value onto the list; a…
In short: An immediate assertion checks a condition the moment the simulator reaches it in procedural code, like a plain if-check. A concurrent assertion checks behaviour over time, sampling signals on a clock edge and spanning one or more cycles. Use immediate for a quick single-point check, and concurrent for anything that involves “on the…
In short: To generate an array of unique random values in SystemVerilog, mark the array rand and add one unique constraint: constraint c { unique {arr}; }. The solver then fills every element with a different value. You can also list extra values inside the braces to keep those out of the set, which is…
In short: When you need an array of distinct values in a mixed order but do not need full randomness, you can skip constraints. Fill the array with known distinct values, such as the index itself, then call the built in shuffle() method to rearrange them. The result has no repeats and a random order,…
In short: rand_mode() turns the random nature of a variable on or off, and constraint_mode() turns a constraint block on or off, both at run time. Call obj.rand_mode(0) to freeze all random variables or obj.var.rand_mode(0) for a single one; a frozen variable keeps its current value through randomize. Call obj.constraint_mode(0) to disable all constraints or…
In short: An assertion is a small rule that describes how a design should behave. If the design breaks the rule during simulation, the assertion fails and points you straight to the problem. The big advantages are early bug detection, better visibility into what went wrong, reuse in both simulation and formal tools, and a…