In the ever-evolving world of chip design, where circuits dance with logic and transistors tango with electrons, stands a breed of unsung heroes: the ASIC verification engineers. These digital detectives, armed with their arsenal of tests, hunt down bugs with the zeal of Indiana Jones and the precision of a Swiss watchmaker. Today, we delve…
As an experienced ASIC verification engineer, I’ve seen firsthand the importance of a thorough verification plan. A well-crafted verification plan can help to ensure that your design is bug-free and ready for production, while a poorly-crafted plan can lead to missed deadlines, costly rework, and even product recalls. In this blog post, I’ll discuss the…
Here in this overriding of constraint if we will have the same constraint name in the parent class as well as child class then we can say that our constraint is overridden in the child class. Let us understand through an example: In the above example, you can observe that the EDA tool will try…
The built-in class randomize method operates exclusively on class member variables. Using classes to model the data to be randomized is a powerful mechanism that enables the creation of generic, reusable objects containing random variables and constraints that can be later extended, inherited, constrained, overridden, enabled, disabled, and merged with or separated from other objects….
It’s easy to get the first cycle of random numbers by pushing values on a list in post_randomize() and adding a constraint that keeps the values in the list excluded from the next solution. The real problem is knowing when to start the cycle over by clearing the list. If the exact number of possible…
Nowadays in many verification scenarios, it requires to create a set of random instructions or addresses with each unique value or we can say that no repeating values, usually represented as elements in a dynamic array. Earlier versions of SystemVerilog required you to use either nested foreach loops to constraint all combinations of array elements…
Without using Random variable and constraint, you can generate array of random unique values using below code, but it is not fully random.
rand_mode(): Variables who is having random nature declared as rand or randc can be turned on or off dynamically by using an in-built method called rand_mode(). It can be called either function or task. In the below example, you can see that how rand_mode we are going to use to disabled and enabled all variables….
In below example we can understand how we can enable or disable a specific constraint whenever we need to do.
Randcase: Randcase is a case statement that randomly selects one of its branches just like a case statement in Verilog but here as its randcase so it will pick statements randomly. Randcase can be used in class or modules. The randcase item expressions are non-negative integral values that constitute the branch weights. An item weight…