Why SystemVerilog Randomization Fails (and How to Debug It)
randomize() returned 0? Six causes of SystemVerilog randomization failure, how to read the VCS solver log, a 5-minute triage, and a demo with real logs.
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From RTL to Reality: Inside Hardik Trivedi’s Design Verification Journey
In the fast-moving business of chip design, where logic and silicon come together to power the devices we rely on every day, a group of quiet problem solvers does the careful work behind the scenes: ASIC verification engineers. These are the people who chase down bugs before a chip ever reaches production, testing every path…
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How to Build a Strong Verification Plan
In short: A verification plan is the map for the whole effort. It lists every feature to check, ranks them by risk, matches each to the right stimulus and technique, and ties coverage goals and a schedule to them so problems appear early. Read the spec first, blend random, directed, and environment-driven stimulus, track coverage…
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Constraint Override in System Verilog
In short: A constraint override happens when a child class declares a constraint with the same name as one in its parent. The child version replaces the parent version, so the solver uses only the child rule. If instead the child uses a different name, both constraints stay active and must be satisfied together, and…
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randomize() Vs std::randomize()
In short: The class method randomize() assigns random values to the rand and randc members of an object, using that class’s constraints. The scope function std::randomize() does the same job but for plain variables in the current scope, with no class needed. Use randomize() when your random data lives in a class with reusable constraints;…
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Generate randc behavior from rand variable
In short: A randc variable walks through every value in its range once before any value repeats. You can copy that no repeat behaviour with a plain rand variable by keeping a list of values already produced and adding a constraint that excludes them. In post_randomize() you push the new value onto the list; a…
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How to Generate an Array of Unique Random Values in SystemVerilog
In short: To fill an array with values that never repeat, mark the array rand and add one line: constraint c { unique {arr}; }. The solver then gives every element a different value. On an old simulator that doesn’t know unique, use a nested foreach with !=. And if you don’t need the solver…
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Generate the array of unique values without using random and constraints
In short: When you need an array of distinct values in a mixed order but do not need full randomness, you can skip constraints. Fill the array with known distinct values, such as the index itself, then call the built in shuffle() method to rearrange them. The result has no repeats and a random order,…
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rand_mode vs constraint_mode in SystemVerilog: Freeze a Variable or Drop a Rule
In short: rand_mode() turns one random variable on or off. When it’s off, randomize() leaves that variable’s value alone. constraint_mode() turns one constraint block on or off. When it’s off, the solver ignores that rule. They are independent: freezing a variable does not switch off the constraints that use it, which is why randomize() often…
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Enable/Disable specific constraints
In short: To enable or disable one specific constraint, call constraint_mode() on the named block, not on the whole object: obj.block_name.constraint_mode(0) switches that one rule off, and obj.block_name.constraint_mode(1) switches it back on. Every other constraint keeps working. Called with no argument on a named block it returns the current state, 1 for enabled and 0…
