@event Vs wait(event.triggered) in SystemVerilog

ByThe Art of Verification

SystemVerilog supports two ways through which we can wait for a particular event to be triggered. So let’s understand what is the exact difference between those two ways of event trigger with the following example. An event trigger ->e is an instantaneous event. The event control @e has to execute and block the current process…

Directed Testing Vs Constraint Random Verification

ByThe Art of Verification

Directed Verification Technique with a set of directed tests is extremely time-consuming and difficult to maintain for more complex designs to verify. Directed tests only cover scenarios that have been anticipated by the verification team by going through specifications, This can lead to costly re-spins and still, there are chances of missing time to market…