In the ever-evolving world of chip design, where circuits dance with logic and transistors tango with electrons, stands a breed of unsung heroes: the ASIC verification engineers. These digital detectives, armed with their arsenal of tests, hunt down bugs with the zeal of Indiana Jones and the precision of a Swiss watchmaker. Today, we delve…
In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an alternative method involves using a multiplied version of the reference clock. This blog post delves into the intricacies of handling clock…
Formal verification and functional verification are two complementary approaches to ASIC verification. Formal verification uses mathematical methods to prove that a design meets its specifications, while functional verification uses simulations to test the design against a variety of scenarios. Formal verification is more rigorous and can find bugs that functional verification may miss, but it…
As an experienced ASIC verification engineer, I’ve seen firsthand the importance of a thorough verification plan. A well-crafted verification plan can help to ensure that your design is bug-free and ready for production, while a poorly-crafted plan can lead to missed deadlines, costly rework, and even product recalls. In this blog post, I’ll discuss the…
Introduction: In the realm of Design Verification, debugging stands as a crucial process for uncovering and rectifying issues that may compromise the functionality, reliability, and performance of complex chip designs. While the term “debugging” might imply a scientific approach, it is truly an art form that requires a delicate balance of technical expertise, creativity, and…
Introduction Hey there, fellow ASIC Verification enthusiasts! Welcome to our deep dive into the fascinating world of verification excellence. Ever wondered what’s at the heart of it all? It’s our thought process. Yes, that’s right! Our ability to think strategically, creatively, and methodically is what sets us apart. It’s the engine that drives our work,…
In the world of semiconductor design and verification, the Universal Verification Methodology (UVM) has become the industry standard for coverage-driven verification (CDV). CDV aims to ensure that all parts of a design are thoroughly tested by measuring functional as well as code coverage. However, CDV alone may not be enough to guarantee that a design…
As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or around it. Understandably, verification is just as complex and time-consuming as it is for, say, an Arm processor-based project. To…
Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two years. The chip makers want to pack as many functions as possible in their SoCs and provide as many feature additions to…
The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs. Quality is even more critical for highly configurable types of IP because customers license it specifically to address the unique requirements of their systems and markets. The on-chip interconnect fabric is perhaps the…