Enable/Disable specific constraints:
In below example we can understand how we can enable or disable a specific constraint whenever we need to do.
Randcase Vs Randsequence in Systemverilog
Randcase: Randcase is a case statement that randomly selects one of its branches just like a case statement in Verilog but here as its randcase so it will pick statements randomly. Randcase can be used in class or modules. The randcase item expressions are non-negative integral values that constitute the branch weights. An item weight…
@event Vs wait(event.triggered) in SystemVerilog
SystemVerilog supports two ways through which we can wait for a particular event to be triggered. So let’s understand what is the exact difference between those two ways of event trigger with the following example. An event trigger ->e is an instantaneous event. The event control @e has to execute and block the current process…
Mailbox in System Verilog
While learning System Verilog you always thought like How do you pass information between two threads/processes? The solution is a SystemVerilog mailbox. From a hardware point of view, the easiest way to think about a mailbox is that it is just a FIFO, with a source and sink. The source puts data into the mailbox,…
Weighted Distribution in System Verilog
In constraint random verification, it may take a long time for a particular corner case to be generated which scenario we never thought. Sometimes even after running test-case regression for N number of time corner case may not be generated and you may see holes in functional coverage. To resolve this issue you can use…
Directed Testing Vs Constraint Random Verification
Directed Verification Technique with a set of directed tests is extremely time-consuming and difficult to maintain for more complex designs to verify. Directed tests only cover scenarios that have been anticipated by the verification team by going through specifications, This can lead to costly re-spins and still, there are chances of missing time to market…
System Verilog Assertion Binding (SVA Bind)
Nowadays we use to deal with modules of Verilog or VHDL or a combination of both. Mostly verification engineers are not allowed to modify these modules. But still, SVA addition to these modules is required, and easy to verify a lot of RTL functionality. How can you add SVA to these modules? Let’s find out…
Semaphore in SystemVerilog:
A semaphore allows you to control access to a resource. Conceptually, a semaphore is a bucket. When a semaphore is allocated, a bucket that contains a fixed number of keys is created. Processes using semaphores must first procure a key from the bucket before they can continue to execute. If a specific process requires a…
Different Array Types and Queues in System Verilog
Dynamic Array: Usage of dynamic array when user to allocate its size for storage during run time. Dynamic array store a contiguous collection of data. The array indexing should be always integer type. To allocate the size of a dynamic array, we have to use a new[] operator. Example: How to resize a dynamic array?…
Encapsulation:
Many times we might use the Base Class or Base Class library provided by third party sources. By default, These Class Members are Public in nature. It means these Class Members can be accessed directly from outside of that Class. But sometimes Base Class providers may restrict how others can access the Class members as…