From RTL to Reality: Unlocking the Secrets of Hardik’s Design Verification Odyssey
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From RTL to Reality: Unlocking the Secrets of Hardik’s Design Verification Odyssey

In the ever-evolving world of chip design, where circuits dance with logic and transistors tango with electrons, stands a breed of unsung heroes: the ASIC verification engineers. These digital detectives, armed with their arsenal of tests, hunt down bugs with the zeal of Indiana Jones and the precision of a Swiss watchmaker. Today, we delve…

Decoding the Art of Handling Clock Signals: Multiplication over Division
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Decoding the Art of Handling Clock Signals: Multiplication over Division

In the realm of digital design, clock signals play a pivotal role in synchronizing the operations of various components. While clock division is a common approach for generating clock signals with different frequencies, an alternative method involves using a multiplied version of the reference clock. This blog post delves into the intricacies of handling clock…

Formal Verification vs Functional Verification: A Tale of Two Approaches
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Formal Verification vs Functional Verification: A Tale of Two Approaches

Formal verification and functional verification are two complementary approaches to ASIC verification. Formal verification uses mathematical methods to prove that a design meets its specifications, while functional verification uses simulations to test the design against a variety of scenarios. Formal verification is more rigorous and can find bugs that functional verification may miss, but it…

Unveiling the Masterpiece: The Art of Crafting an Unbeatable Verification Plan
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Unveiling the Masterpiece: The Art of Crafting an Unbeatable Verification Plan

As an experienced ASIC verification engineer, I’ve seen firsthand the importance of a thorough verification plan. A well-crafted verification plan can help to ensure that your design is bug-free and ready for production, while a poorly-crafted plan can lead to missed deadlines, costly rework, and even product recalls. In this blog post, I’ll discuss the…

Debugging is an Art, not a Science in Design Verification: Embracing the Human Touch
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Debugging is an Art, not a Science in Design Verification: Embracing the Human Touch

Introduction: In the realm of Design Verification, debugging stands as a crucial process for uncovering and rectifying issues that may compromise the functionality, reliability, and performance of complex chip designs. While the term “debugging” might imply a scientific approach, it is truly an art form that requires a delicate balance of technical expertise, creativity, and…

5 Key Elements to Master Verification Excellence: The Transformative Power of Rethinking Design and Thought Process
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5 Key Elements to Master Verification Excellence: The Transformative Power of Rethinking Design and Thought Process

Introduction Hey there, fellow ASIC Verification enthusiasts! Welcome to our deep dive into the fascinating world of verification excellence. Ever wondered what’s at the heart of it all? It’s our thought process. Yes, that’s right! Our ability to think strategically, creatively, and methodically is what sets us apart. It’s the engine that drives our work,…

Importance of Stress Verification !!
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Importance of Stress Verification !!

In the world of semiconductor design and verification, the Universal Verification Methodology (UVM) has become the industry standard for coverage-driven verification (CDV). CDV aims to ensure that all parts of a design are thoroughly tested by measuring functional as well as code coverage. However, CDV alone may not be enough to guarantee that a design…

How to Verify Complex RISC-V–based Designs?

How to Verify Complex RISC-V–based Designs?

As RISC-V processor development matures and the core’s usage in SoCs and microcontrollers grows, engineering teams face new verification challenges related not to the RISC-V core itself but rather to the system based on or around it. Understandably, verification is just as complex and time-consuming as it is for, say, an Arm processor-based project. To…

Formal Verification: Where to use it and Why?

Formal Verification: Where to use it and Why?

With innovations in technologies and methodology, the benefits of formal functional verification apply in many more areas. If we understand the characteristics of areas with high formal applicability, we can identify not only which blocks are good candidates, but also what portions or functionalities of the blocks will give the greatest return on the time…