Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two years. The chip makers want to pack as many functions as possible in their SoCs and provide as many feature additions to…
The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs. Quality is even more critical for highly configurable types of IP because customers license it specifically to address the unique requirements of their systems and markets. The on-chip interconnect fabric is perhaps the…
Interrupt handling is a well-known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many IP blocks as part of it. In some way or other Interrupts are used to act as the sideband signals of the Design/IP Blocks & most of the time it’s not the part of the main…
How to connect the DUT to the UVM Testbench?? In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form of signals/wire/nets at all levels in the DUT as well as in TestBench. But this is not the case in the latest “Constrained Random Verification Methodology” like…
Introduction As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various wireless modules, and processors that use new bus architectures to communicate with them. They can also have various interfaces like I2C, PCM, I2S, AHB, etc. Yet, these SoC components will share a single clock control unit. This module generates…
Today, let’s delve into UVM RAL: What it is, its importance, and the structure it entails. The discussion will cover the definition of RAL, the reasons for its necessity, and an overview of the UVM RAL framework design. It is essential to understand that our Device Under Test (DUT), whether an SoC or Subsystem, contains…
As AXI protocol and Cache Coherency are commonly used concepts these days in almost each and every complex SoC’s so knowledge of those concepts are must for everyone to know how it works. All AXI and Cache Coherency concepts are guided by one of the most experienced Verification Engineer in the industry Mr. Rahul Bhardwaj…
In the intricate world of ASIC Verification, the SOC Verification Flow is a cornerstone process that necessitates both expertise and experience. Many people may not fully understand what sets a system-on-chip (SoC) apart from other semiconductor devices. Within the realm of electronic design automation (EDA), the term “SoC” is often used without a clear definition or explanation…