Creative ways to solve problems
The streaming operator uses the terminology pack when you take multiple variables and stream them into a single variable. And conversely, unpack is when you stream a single variable into multiple variables. Let’s understand through the below example:
Continue ReadingInheritance in SystemVerilog is the most commonly used principle of Object Oriented Programming (OOP) that facilitates reuse. It’s called Inheritance because it creates new classes taking all the existing Properties and Methods from the Base Class or Super Class. The new Class is called Extended Class or Derived Class. The Extended Class contains everything declared […]
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Coverage is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of constrained random testbenches. Types of coverage metrics – Let’s understand the types of coverage more deeply Code […]
Continue ReadingPlus args are command-line switches supported by the simulator. Usually, they are application-specific. As per SystemVerilog LRM arguments beginning with the ‘+’ character will be available using the $test$plusargs and $value$plusargs PLI APIs. Plus args are very useful in controlling many things in your environment like controlling your debug mode or setting a value like […]
Continue ReadingA difference between ifdef and plusarg is that ifdef removes/adds code in compilation itself, while plusarg will compile the entire code suite. While using ifdef, one needs to re-compile in order to change the macro argument. On the other hand, the plusarg code is compiled irrespective of the command line argument
Continue ReadingHere in this overriding of constraint if we will have the same constraint name in the parent class as well as child class then we can say that our constraint is overridden in the child class. Let us understand through an example: In the above example, you can observe that the EDA tool will try […]
Continue ReadingThe built-in class randomize method operates exclusively on class member variables. Using classes to model the data to be randomized is a powerful mechanism that enables the creation of generic, reusable objects containing random variables and constraints that can be later extended, inherited, constrained, overridden, enabled, disabled, and merged with or separated from other objects. […]
Continue ReadingFunctional Coverage is very important in Test Bench Development. It always gives us confidence in covered items listed on the verification plan. Usually, the goal of a verification engineer is to ensure that the design behaves correctly in its real environment according to specifications. Defining a coverage model is very important for any test bench […]
Continue ReadingIt’s easy to get the first cycle of random numbers by pushing values on a list in post_randomize() and adding a constraint that keeps the values in the list excluded from the next solution. The real problem is knowing when to start the cycle over by clearing the list. If the exact number of possible […]
Continue ReadingImmediate assertions use expressions and are executed like a statement in a procedural block. They are not temporal in nature and are evaluated immediately when executed. Immediate assertions are used only in dynamic simulations. Following is an example of a simple immediate assertion that checks “if x and y are always equal”: Concurrent assertions are temporal […]
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