In short: The streaming operator in SystemVerilog reshapes data between a single vector and a group of values. Use >> to stream left to right and << to stream right to left. “Pack” squeezes several fields into one wide vector or byte queue, and “unpack” spreads a vector back out into fields. It is the…
In short: Inheritance lets one class (the child) reuse the fields and methods of another class (the parent) using the extends keyword. The child gets everything the parent has, can add new members, and can replace a parent method by overriding it. Mark methods virtual so the right version runs when you call through a…
In short: There are two families of coverage metrics. Code coverage is measured automatically by the simulator and tells you how much of the RTL was exercised (statement, block, branch, condition or expression, toggle, and FSM). Functional coverage is written by you and tells you whether the features from the test plan were actually tested….
In short: Plusargs are command line switches that a simulator passes into your SystemVerilog code at run time. You read them with two system functions: $test$plusargs checks whether a flag is present, and $value$plusargs reads a value that follows a flag. Because they are read at run time, you can change test name, seed, or…
In short: The difference between ifdef and plusargs is when they act. An ifdef is a compile time macro: it decides which code is built into the image, so changing it needs a recompile, but the excluded code is truly gone. A plusarg is a run time switch: the whole design is compiled once and…
In short: A constraint override happens when a child class declares a constraint with the same name as one in its parent. The child version replaces the parent version, so the solver uses only the child rule. If instead the child uses a different name, both constraints stay active and must be satisfied together, and…
In short: The class method randomize() assigns random values to the rand and randc members of an object, using that class’s constraints. The scope function std::randomize() does the same job but for plain variables in the current scope, with no class needed. Use randomize() when your random data lives in a class with reusable constraints;…
In short: Functional coverage options in SystemVerilog tune how a covergroup collects and reports data. The everyday ones are option.comment to label a group, option.per_instance to report each instance separately, option.at_least to set how many hits a bin needs, option.cross_num_print_missing to show empty bins, and option.goal to set the target percentage. They change reporting, not…
In short: A randc variable walks through every value in its range once before any value repeats. You can copy that no repeat behaviour with a plain rand variable by keeping a list of values already produced and adding a constraint that excludes them. In post_randomize() you push the new value onto the list; a…
In short: An immediate assertion checks a condition the moment the simulator reaches it in procedural code, like a plain if-check. A concurrent assertion checks behaviour over time, sampling signals on a clock edge and spanning one or more cycles. Use immediate for a quick single-point check, and concurrent for anything that involves “on the…